Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor
HORI; RYOICHI, MIYAZAWA; KAZUYUKI, KIZAKI; TAKESHI, UCHIYAMA; HIROYUKI, IWAI; HIDETOSHI, AOYAGI; HIDETOMO, OGUCHI; SATOSHI, TAKEKUMA; TOSHITUGU, MATSUURA; HIROMI, TAKAHASHI; YASUSHI, II; HARUO, NAKAMURA; HISASHI, KOYAMA; YOSHIHISA, MURANAKA; MASAYA, SAKOMURA; SHIGETOSHI, ISHIHARA; MASAMICHI
Year of Publication 08.09.1998
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Year of Publication 08.09.1998
Patent
Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor
HORI; RYOICHI, MIYAZAWA; KAZUYUKI, KIZAKI; TAKESHI, UCHIYAMA; HIROYUKI, IWAI; HIDETOSHI, AOYAGI; HIDETOMO, OGUCHI; SATOSHI, TAKEKUMA; TOSHITUGU, MATSUURA; HIROMI, TAKAHASHI; YASUSHI, II; HARUO, NAKAMURA; HISASHI, KOYAMA; YOSHIHISA, MURANAKA; MASAYA, SAKOMURA; SHIGETOSHI, ISHIHARA; MASAMICHI
Year of Publication 20.06.1995
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Year of Publication 20.06.1995
Patent