A 7T-SRAM With Data-Write Technique by Capacitive Coupling
Takashima, Daisaburo, Endo, Masato, Shimazaki, Kazuhiro, Sai, Manabu, Tanino, Masaaki
Published in IEEE journal of solid-state circuits (01.02.2019)
Published in IEEE journal of solid-state circuits (01.02.2019)
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Journal Article
A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes
Shiga, H., Takashima, D., Shiratake, S., Hoya, K., Miyakawa, T., Ogiwara, R., Fukuda, R., Takizawa, R., Hatsuda, K., Matsuoka, F., Nagadomi, Y., Hashimoto, D., Nishimura, H., Hioka, T., Doumae, S., Shimizu, S., Kawano, M., Taguchi, T., Watanabe, Y., Fujii, S., Ozaki, T., Kanaya, H., Kumura, Y., Shimojo, Y., Yamada, Y., Minami, Y., Shuto, S., Yamakawa, K., Yamazaki, S., Kunishima, I., Hamamoto, T., Nitayama, A., Furuyama, T.
Published in IEEE journal of solid-state circuits (01.01.2010)
Published in IEEE journal of solid-state circuits (01.01.2010)
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Journal Article
Conference Proceeding
An Embedded DRAM Technology for High-Performance NAND Flash Memories
Takashima, D., Noguchi, M., Shibata, N., Kanda, K., Sukegawa, H., Fujii, S.
Published in IEEE journal of solid-state circuits (01.02.2012)
Published in IEEE journal of solid-state circuits (01.02.2012)
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Journal Article