3D monolithic integration: Technological challenges and electrical results
Vinet, M., Batude, P., Tabone, C., Previtali, B., LeRoyer, C., Pouydebasque, A., Clavelier, L., Valentian, A., Thomas, O., Michaud, S., Sanchez, L., Baud, L., Roman, A., Carron, V., Nemouchi, F., Mazzocchi, V., Grampeix, H., Amara, A., Deleonibus, S., Faynot, O.
Published in Microelectronic engineering (01.04.2011)
Published in Microelectronic engineering (01.04.2011)
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3DVLSI with CoolCube process: An alternative path to scaling
Batude, P., Fenouillet-Beranger, C., Pasini, L., Lu, V., Deprat, F., Brunet, L., Sklenard, B., Piegas-Luce, F., Casse, M., Mathieu, B., Billoint, O., Cibrario, G., Turkyilmaz, O., Sarhan, H., Thuries, S., Hutin, L., Sollier, S., Widiez, J., Hortemel, L., Tabone, C., Samson, M.-P, Previtali, B., Rambal, N., Ponthenier, F., Mazurier, J., Beneyton, R., Bidaud, M., Josse, E., Petitprez, E., Rozeau, O., Rivoire, M., Euvard-Colnat, C., Seignard, A., Fournel, F., Benaissa, L., Coudrain, P., Leduc, P., Hartmann, J.-M, Besson, P., Kerdiles, S., Bout, C., Nemouchi, F., Royer, A., Agraffeil, C., Ghibaudo, G., Signamarcheix, T., Haond, M., Clermidy, F., Faynot, O., Vinet, M.
Published in 2015 Symposium on VLSI Technology (VLSI Technology) (01.06.2015)
Published in 2015 Symposium on VLSI Technology (VLSI Technology) (01.06.2015)
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First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers
Brunet, L., Batude, P., Fenouillet-Beranger, C., Besombes, P., Hortemel, L., Ponthenier, F., Previtali, B., Tabone, C., Royer, A., Agraffeil, C., Euvrard-Colnat, C., Seignard, A., Morales, C., Fournel, F., Benaissa, L., Signamarcheix, T., Besson, P., Jourdan, M., Kachtouli, R., Benevent, V., Hartmann, J.-M, Comboroure, C., Allouti, N., Posseme, N., Vizioz, C., Arvet, C., Barnola, S., Kerdiles, S., Baud, L., Pasini, L., Lu, C.-M V., Deprat, F., Toffoli, A., Romano, G., Guedj, C., Delaye, V., Boeuf, F., Faynot, O., Vinet, M.
Published in 2016 IEEE Symposium on VLSI Technology (01.06.2016)
Published in 2016 IEEE Symposium on VLSI Technology (01.06.2016)
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Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond
Andrieu, F, Weber, O, Mazurier, J, Thomas, O, Noel, J.-P, Fenouillet-Béranger, C, Mazellier, J.-P, Perreau, P, Poiroux, T, Morand, Y, Morel, T, Allegret, S, Loup, V, Barnola, S, Martin, F, Damlencourt, J.-F, Servin, I, Cassé, M, Garros, X, Rozeau, O, Jaud, M.-A, Cibrario, G, Cluzel, J, Toffoli, A, Allain, F, Kies, R, Lafond, D, Delaye, V, Tabone, C, Tosti, L, Brévard, L, Gaud, P, Paruchuri, V, Bourdelle, K K, Schwarzenbach, W, Bonnin, O, Nguyen, B.-Y, Doris, B, Bœuf, F, Skotnicki, T, Faynot, O
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs
Koyama, M., Cassé, M., Coquand, R., Barraud, S., Vizioz, C., Comboroure, C., Perreau, P., Maffini-Alvaro, V., Tabone, C., Tosti, L., Barnola, S., Delaye, V., Aussenac, F., Ghibaudo, G., Iwai, H., Reimbold, G.
Published in Solid-state electronics (01.06.2013)
Published in Solid-state electronics (01.06.2013)
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Histological evolution of recurrent basal cell carcinoma and therapeutic implications for incompletely excised lesions
Boulinguez, S., Grison-Tabone, C., Lamant, L., Valmary, S., Viraben, R., Bonnetblanc, J.M., Bédane, C.
Published in British journal of dermatology (1951) (01.09.2004)
Published in British journal of dermatology (1951) (01.09.2004)
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On the use of a localized STRASS technique to obtain highly tensile strained Si regions in advanced FDSOI CMOS devices
Bonnevialle, A., Reboh, S., Le Royer, C., Morand, Y., Hartmann, J.-M., Rouchon, D., Pedini, J.-M., Tabone, C., Rambal, N., Payet, A., Plantier, C., Boeuf, F., Haond, M., Claverie, A., Vinet, M.
Published in Physica status solidi. C (01.12.2016)
Published in Physica status solidi. C (01.12.2016)
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Investigations of the ionizing radiation induced effects in ultra-thin strained-silicon layers on insulator using confocal microscopy measurements
Gaillardin, M., Girard, S., Ouerdane, Y., Boukenter, A., Andrieu, F., Tabone, C., Faynot, O.
Published in Journal of non-crystalline solids (15.04.2011)
Published in Journal of non-crystalline solids (15.04.2011)
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Transistors on hybrid UTBB/Bulk substrates fabricated by local internal BOX dissolution
Nguyen, P., Andrieu, F., Cassé, M., Tabone, C., Perreau, P., Lafond, D., Dansas, H., Tosti, L., Veytizou, C., Landru, D., Kononchuk, O., Guiot, E., Nguyen, B.-Y., Faynot, O., Poiroux, T.
Published in Solid-state electronics (01.12.2013)
Published in Solid-state electronics (01.12.2013)
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High performance 70 nm gate length germanium-on-insulator pMOSFET with high- k/metal gate
Romanjek, K., Hutin, L., Le Royer, C., Pouydebasque, A., Jaud, M.-A., Tabone, C., Augendre, E., Sanchez, L., Hartmann, J.-M., Grampeix, H., Mazzocchi, V., Soliveres, S., Truche, R., Clavelier, L., Scheiblin, P., Garros, X., Reimbold, G., Vinet, M., Boulanger, F., Deleonibus, S.
Published in Solid-state electronics (01.07.2009)
Published in Solid-state electronics (01.07.2009)
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High mobility CMOS: First demonstration of planar GeOI p-FETs with SOI n-FETs
Le Royer, C., Damlencourt, J.-F., Vincent, B., Romanjek, K., Le Cunff, Y., Grampeix, H., Mazzocchi, V., Carron, V., Némouchi, F., Hartmann, J.-M., Arvet, C., Vizioz, C., Tabone, C., Hutin, L., Batude, P., Vinet, M.
Published in Solid-state electronics (01.05.2011)
Published in Solid-state electronics (01.05.2011)
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High- \kappa and Metal-Gate pMOSFETs on GeOI Obtained by Ge Enrichment: Analysis of ON and OFF Performances
Le Royer, C., Vincent, B., Clavelier, L., Damlencourt, J.-F., Tabone, C., Batude, P., Blachier, D., Truche, R., Campidelli, Y., Nguyen, Q.T., Cristoloveanu, S., Soliveres, S., Le Carval, G., Boulanger, F., Billon, T., Bensahel, D., Deleonibus, S.
Published in IEEE electron device letters (01.06.2008)
Published in IEEE electron device letters (01.06.2008)
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105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers
LE RAYER, C, CLAVELIER, L, LE CARVAL, G, TRUCHE, R, POUYDEBASQUE, A, VINET, M, DELEONIBUS, S, TABONE, C, ROMANJEK, K, DEGUET, C, SANCHEZ, L, HARTMANN, J.-M, ROURE, M.-C, GRAMPEIX, H, SOLIVERES, S
Published in Solid-state electronics (01.09.2008)
Published in Solid-state electronics (01.09.2008)
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Experimental Evidence of Sidewall Enhanced Transport Properties of Mesa-Isolated (001) Germanium-On-Insulator pMOSFETs
Pouydebasque, A., Romanjek, K., Le Royer, C., Tabone, C., Previtali, B., Allain, F., Augendre, E., Hartmann, J.-M., Grampeix, H., Vinet, M.
Published in IEEE transactions on electron devices (01.12.2009)
Published in IEEE transactions on electron devices (01.12.2009)
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Dual strained channel CMOS in FDSOI architecture: New insights on the device performance
Le Royer, C., Cassé, M., Cooper, D., Andrieu, F., Weber, O., Brevard, L., Perreau, P., Damlencourt, J.-F., Baudot, S., Prévitali, B., Tabone, C., Allain, F., Scheiblin, P., Rauer, C., Figuet, C., Aulnette, C., Daval, N., Nguyen, B.-Y., Bourdelle, K.K., Gyani, J., Valenza, M.
Published in Solid-state electronics (01.11.2011)
Published in Solid-state electronics (01.11.2011)
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High performance low temperature activated devices and optimization guidelines for 3D VLSI integration of FD, TriGate, FinFET on insulator
Pasini, L., Batude, P., Casse, M., Mathieu, B., Sklenard, B., Luce, F. Piegas, Reboh, S., Bernier, N., Tabone, C., Rozeau, O., Martini, S., Fenouillet-Beranger, C., Brunet, L., Audoit, G., Lafond, D., Aussenac, F., Allain, F., Romano, G., Barraud, S., Rambal, N., Barral, V., Hutin, L., Hartmann, J.-M, Besson, P., Kerdiles, S., Haond, M., Ghibaudo, G., Vinet, M.
Published in 2015 Symposium on VLSI Technology (VLSI Technology) (01.06.2015)
Published in 2015 Symposium on VLSI Technology (VLSI Technology) (01.06.2015)
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Balneotherapy, prevention of cognitive decline and care the Alzheimer patient and his family: Outcome of a multidisciplinary workgroup
Secher, M., Soto, M., Gillette, S., Andrieu, S., Villars, H., Vellas, B., Tabone, C., Chareyras, J. -B., Dubois, O., Roques, C. -F., Dubois, B.
Published in The Journal of nutrition, health & aging (01.11.2009)
Published in The Journal of nutrition, health & aging (01.11.2009)
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20nm gate length trigate pFETs on strained SGOI for high performance CMOS
Hutin, L, Cassé, M, Le Royer, C, Damlencourt, J.-F, Pouydebasque, A, Xu, C, Tabone, C, Hartmann, J.-M, Carron, V, Grampeix, H, Mazzocchi, V, Truche, R, Weber, O, Batude, P, Garros, X, Clavelier, L, Vinet, M, Faynot, O
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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