23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture
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Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01.02.2017)
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01.02.2017)
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Conference Proceeding
SUBSTRATE PROCESSING METHOD AND SELECTIVE DEPOSITION METHOD USING THE SAME
LEE, Jeongmin, LEE, Seohyun, KIM, Woohee, CHUNG, SungWoong, KAWK, Junghun, LEE, Jihun
Year of Publication 12.10.2023
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Year of Publication 12.10.2023
Patent
HOSP(R) as a low dielectric material: comparative study against hydrogen silsesquioxane
Sun-Young Kim, Sungwoong Chung, Joohan Shin, Nae Hak Park, Jun Ki Kim, Jin Won Park
Published in ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) (1999)
Published in ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) (1999)
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