Visualization and automatic detection of defect distribution in GaN atomic structure from sampling Moiré phase
Wang, Q H, Ri, S, Tsuda, H, Kodera, M, Suguro, K, Miyashita, N
Published in Nanotechnology (10.11.2017)
Published in Nanotechnology (10.11.2017)
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Journal Article
Visualization and automatic detection of defect distribution in GaN atomic structure from sampling Moiré phase
Wang, Q H, Ri, S, Tsuda, H, Kodera, M, Suguro, K, Miyashita, N
Published in Nanotechnology (10.11.2017)
Published in Nanotechnology (10.11.2017)
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Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI
Morimoto, T., Ohguro, T., Momose, S., Iinuma, T., Kunishima, I., Suguro, K., Katakabe, I., Nakajima, H., Tsuchiaki, M., Ono, M., Katsumata, Y., Iwai, H.
Published in IEEE transactions on electron devices (01.05.1995)
Published in IEEE transactions on electron devices (01.05.1995)
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Improvement of threshold voltage deviation in damascene metal gate transistors
Yagishita, A., Saito, T., Nakajima, K., Inumiya, S., Matsuo, K., Shibata, T., Tsunashima, Y., Suguro, K., Arikado, T.
Published in IEEE transactions on electron devices (01.08.2001)
Published in IEEE transactions on electron devices (01.08.2001)
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High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide
Inaba, S., Okano, K., Matsuda, S., Fujiwara, M., Hokazono, A., Adachi, K., Ohuchi, K., Suto, H., Fukui, H., Shimizu, T., Mori, S., Oguma, H., Murakoshi, A., Itani, T., Iinuma, T., Kudo, T., Shibata, H., Taniguchi, S., Takayanagi, M., Azuma, A., Oyamatsu, H., Suguro, K., Katsumata, Y., Toyoshima, Y., Ishiuchi, H.
Published in IEEE transactions on electron devices (01.12.2002)
Published in IEEE transactions on electron devices (01.12.2002)
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Journal Article
High performance damascene metal gate MOSFETs for 0.1 μm regime
Yagishita, A, Saito, T, Nakajima, K, Inumiya, S, Akasaka, Y, Ozawa, Y, Hieda, K, Tsunashima, Y, Suguro, K, Arikado, T, Okumura, K
Published in IEEE transactions on electron devices (01.05.2000)
Published in IEEE transactions on electron devices (01.05.2000)
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Highly reliable CVD-WSi metal gate electrode for nMOSFETs
Nakajima, K., Nakazawa, H., Sekine, K., Matsuo, K., Saito, T., Katata, T., Suguro, K., Tsunashima, Y.
Published in IEEE transactions on electron devices (01.10.2005)
Published in IEEE transactions on electron devices (01.10.2005)
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Improvement of performance deviation and productivity of MOSFETs with gate length below 30 nm by flash lamp annealing
Nishinohara, K.T., Ito, T., Suguro, K.
Published in IEEE transactions on semiconductor manufacturing (01.08.2004)
Published in IEEE transactions on semiconductor manufacturing (01.08.2004)
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Conference Proceeding
Suppression of SiN-induced boron penetration by using SiH-free silicon nitride films formed by tetrachlorosilane and ammonia
Tanaka, M., Saida, S., Mizushima, I., Inoue, F., Kojima, M., Tanaka, T., Nakanishi, T., Suguro, K., Tsunashima, Y.
Published in IEEE transactions on electron devices (01.09.2002)
Published in IEEE transactions on electron devices (01.09.2002)
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Low-resistance ultrashallow extension formed by optimized flash lamp annealing
Ito, T., Suguro, K., Tamura, M., Taniguchi, T., Ushiku, Y., Iinuma, T., Itani, T., Yoshioka, M., Owada, T., Imaoka, Y., Murayama, H., Kusuda, T.
Published in IEEE transactions on semiconductor manufacturing (01.08.2003)
Published in IEEE transactions on semiconductor manufacturing (01.08.2003)
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Conference Proceeding
Issues and optimization of millisecond anneal process for 45 nm node and beyond
Adachi, K., Ohuchi, K., Aoki, N., Tsujii, H., Ito, T., Itokawa, H., Matsuo, K., Suguro, K., Honguh, Y., Tamaoki, N., Ishimaru, K., Ishiuchi, H.
Published in Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005 (2005)
Published in Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005 (2005)
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Conference Proceeding
Formation mechanism of ultrathin WSiN barrier layer in a W/WNx/Si system
Nakajima, K., Akasaka, Y., Miyano, K., Takahashi, M., Suehiro, S., Suguro, K.
Published in Applied surface science (01.06.1997)
Published in Applied surface science (01.06.1997)
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FinFET: the prospective multi-gate device for future SoC applications
Inaba, S., Okano, K., Izumida, T., Kaneko, A., Kawasaki, H., Yagishita, A., Kanemura, T., Ishida, T., Aoki, N., Ishimaru, K., Suguro, K., Eguchi, K., Tsunashima, Y., Toyoshima, Y., Ishiuchi, H.
Published in 2006 European Solid-State Device Research Conference (01.09.2006)
Published in 2006 European Solid-State Device Research Conference (01.09.2006)
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Conference Proceeding
Stencil mask ion implantation technology
Shibata, T., Suguro, K., Sugihara, K., Nishihashi, T., Fujiyama, J., Sakurada, Y.
Published in IEEE transactions on semiconductor manufacturing (01.05.2002)
Published in IEEE transactions on semiconductor manufacturing (01.05.2002)
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Lithographyless ion implantation technology for agile fab
Nishihashi, T., Kashimoto, K., Fujiyama, J., Sakurada, Y., Shibata, T., Suguro, K., Sugihara, K., Okumura, K., Gotou, T., Saji, N., Tsunoda, M.
Published in IEEE transactions on semiconductor manufacturing (01.11.2002)
Published in IEEE transactions on semiconductor manufacturing (01.11.2002)
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Journal Article
Conference Proceeding
Low-resistivity poly-metal gate electrode durable for high-temperature processing
Akasaka, Y., Suehiro, S., Nakajima, K., Nakasugi, T., Miyano, K., Kasai, K., Oyamatsu, H., Kinugawa, M., Takagi, M.T., Agawa, K., Matsuoka, F., Kakumu, M., Suguro, K.
Published in IEEE transactions on electron devices (01.11.1996)
Published in IEEE transactions on electron devices (01.11.1996)
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Surface Channel Metal Gate Complementary MOS with Light Counter Doping and Single Work Function Gate Electrode
Nishinohara, Kazumi T., Akasaka, Yasushi, Saito, Tomohiro, Yagishita, Atsushi, Murakoshi, Atsushi, Suguro, Kyoichi, Arikado, Tsunetoshi
Published in Japanese Journal of Applied Physics (2001)
Published in Japanese Journal of Applied Physics (2001)
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