Enabling FPGA-as-a-Service in the Cloud with hCODE Platform
ZHAO, Qian, AMAGASAKI, Motoki, IIDA, Masahiro, KUGA, Morihiro, SUEYOSHI, Toshinori
Published in IEICE Transactions on Information and Systems (01.02.2018)
Published in IEICE Transactions on Information and Systems (01.02.2018)
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Journal Article
Three Dimensional FPGA Architecture with Fewer TSVs
AMAGASAKI, Motoki, IKEBE, Masato, ZHAO, Qian, IIDA, Masahiro, SUEYOSHI, Toshinori
Published in IEICE Transactions on Information and Systems (01.02.2018)
Published in IEICE Transactions on Information and Systems (01.02.2018)
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Journal Article
A 3D FPGA Architecture to Realize Simple Die Stacking
Amagasaki, Motoki, Zhao, Qian, Iida, Masahiro, Kuga, Morihiro, Sueyoshi, Toshinori
Published in IPSJ Transactions on System LSI Design Methodology (01.01.2015)
Published in IPSJ Transactions on System LSI Design Methodology (01.01.2015)
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Journal Article
An Easily Testable Routing Architecture and Prototype Chip
INOUE, Kazuki, KOGA, Masahiro, AMAGASAKI, Motoki, IIDA, Masahiro, ICHIDA, Yoshinobu, SAJI, Mitsuro, IIDA, Jun, SUEYOSHI, Toshinori
Published in IEICE transactions on information and systems (01.01.2012)
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Published in IEICE transactions on information and systems (01.01.2012)
Journal Article
Clustering technique to reduce chip area and delay for FPGA
Kobata, Masaki, Iida, Masahiro, Sueyoshi, Toshinori
Published in Electronics & Communications in Japan. Part 2, Electronics (01.06.2007)
Published in Electronics & Communications in Japan. Part 2, Electronics (01.06.2007)
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Journal Article
Early DoS/DDoS Detection Method using Short-term Statistics
Oshima, Shunsuke, Nakashima, Takuo, Sueyoshi, Toshinori
Published in 2010 International Conference on Complex, Intelligent and Software Intensive Systems (01.02.2010)
Published in 2010 International Conference on Complex, Intelligent and Software Intensive Systems (01.02.2010)
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Conference Proceeding
A 3D FPGA Architecture to Realize Simple Die Stacking
Amagasaki, Motoki, Zhao, Qian, Iida, Masahiro, Kuga, Morihiro, Sueyoshi, Toshinori
Published in Information and Media Technologies (01.01.2015)
Published in Information and Media Technologies (01.01.2015)
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Journal Article
A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory
Qian Zhao, Yanagida, Kyosei, Amagasaki, Motoki, Iida, Masahiro, Kuga, Morihiro, Sueyoshi, Toshinori
Published in 2014 24th International Conference on Field Programmable Logic and Applications (FPL) (01.09.2014)
Published in 2014 24th International Conference on Field Programmable Logic and Applications (FPL) (01.09.2014)
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Conference Proceeding
Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration
Ichinomiya, Yoshihiro, Tanoue, Shiro, Amagasaki, Motoki, Iida, Masahiro, Kuga, Morihiro, Sueyoshi, Toshinori
Published in 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (01.01.2010)
Published in 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (01.01.2010)
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Conference Proceeding
Three-dimensional stacking FPGA architecture using face-to-face integration
Hamada, Tetsuro, Qian Zhao, Amagasaki, Motoki, Iida, Masahiro, Kuga, Morihiro, Sueyoshi, Toshinori
Published in 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC) (01.10.2013)
Published in 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC) (01.10.2013)
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Conference Proceeding
Defect-robust FPGA architectures for intellectual property cores in system LSI
Amagasaki, Motoki, Inoue, Kazuki, Qian Zhao, Iida, Masahiro, Kuga, Morihiro, Sueyoshi, Toshinori
Published in 2013 23rd International Conference on Field programmable Logic and Applications (01.09.2013)
Published in 2013 23rd International Conference on Field programmable Logic and Applications (01.09.2013)
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Conference Proceeding