Search Results - "Srikanth Arekapudi" :: K.UTB vyhledávací portál

Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor

by Sathe, V. S., Arekapudi, S., Ishii, A., Ouyang, C., Papaefthymiou, M. C., Naffziger, S.
Published in IEEE journal of solid-state circuits (01.01.2013)

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Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS

by McIntyre, H., Arekapudi, S., Busta, E., Fischer, T., Golden, M., Horiuchi, A., Meneghini, T., Naffziger, S., Vinh, J.
Published in IEEE journal of solid-state circuits (01.01.2012)

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Using hardware to configure a load-balanced switch

by Srikanth Arekapudi, Chuang, S.-T., Keslassy, I., McKeown, N.
Published in IEEE MICRO (01.01.2005)

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Carrizo: A High Performance, Energy Efficient 28 nm APU

by Munger, Benjamin, Akeson, David, Arekapudi, Srikanth, Burd, Tom, Fair, Harry R., Farrell, Jim, Johnson, Dave, Krishnan, Guhan, McIntyre, Hugh, McLellan, Edward, Naffziger, Samuel, Schreiber, Russell, Sundaram, Sriram, White, Jonathan, Wilcox, Kathryn
Published in IEEE journal of solid-state circuits (01.01.2016)

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TASK ACTIVATION FOR ACCELERATED DEEP LEARNING

by MICHAEL MORRISON, SRIKANTH AREKAPUDI, MICHAEL EDWIN JAMES, GARY R LAUTERBACH, LIE SEAN
Year of Publication 29.07.2021

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DATA FLOW TRIGGER TASK FOR ACCELERATED DEEP LEARNING

by MICHAEL MORRISON, SRIKANTH AREKAPUDI, MICHAEL EDWIN JAMES, GARY R LAUTERBACH, LIE SEAN
Year of Publication 29.07.2021

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ACCELERATED DEEP LEARNING

by MICHAEL MORRISON, SRIKANTH AREKAPUDI, MICHAEL EDWIN JAMES, GARY R LAUTERBACH, LIE SEAN
Year of Publication 27.05.2021

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NEURON SMEARING FOR ACCELERATED DEEP LEARNING

by MICHAEL MORRISON, SRIKANTH AREKAPUDI, MICHAEL EDWIN JAMES, GARY R LAUTERBACH, LIE SEAN
Year of Publication 24.12.2020

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Resonant clock design for a power-efficient high-volume x86-64 microprocessor

by Sathe, V., Arekapudi, S., Ouyang, C., Papaefthymiou, M., Ishii, A., Naffziger, S.
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)

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40-Entry unified out-of-order scheduler and integer execution unit for the AMD Bulldozer x86-64 core

by Golden, M, Arekapudi, S, Vinh, J
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)

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Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU

by Fischer, T, Arekapudi, S, Busta, E, Dietz, C, Golden, M, Hilker, S, Horiuchi, A, Hurd, K A, Johnson, D, McIntyre, H, Naffziger, S, Vinh, J, White, J, Wilcox, K
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)

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