Search Results - "Spagna Fulvio" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

High performance interconnect

High performance interconnect

by Jue Darren S, Iyer Sitaraman V, Hum Herbert H, Willey Jeff, Gupta Ashish, Iyer Venkatraman, Swanson Jeffrey C, Blankenship Robert G, Das Sharma Debendra, Geetha Vedaraman, Safranek Robert J, Shah Rahul R, Das Abhishek, Maddox Robert A, Fahim Bahaa, Kumar Arvind A, Spink Aaron T, Nale William Harry, Johnson Simon P, Beers Robert, Liu Yen-Cheng, Spagna Fulvio, Ramanujan Raj K, Dhillon Yuvraj S
Year of Publication 18.04.2017

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Patent

PHASE DETECTOR ARCHITECTURE FOR PHASE ERROR ESTIMATING AND ZERO PHASE RESTARTING

PHASE DETECTOR ARCHITECTURE FOR PHASE ERROR ESTIMATING AND ZERO PHASE RESTARTING

by FULVIO SPAGNA, ROBERT B. STASZEWSKI
Year of Publication 27.10.2003

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Patent

Phase detector architecture for phase error estimating and zero phase restarting

Phase detector architecture for phase error estimating and zero phase restarting

by STASZEWSKI, ROBERT B, SPAGNA, FULVIO
Year of Publication 21.08.2003

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Patent

Phase detector architecture for phase error estimating and zero phase restarting

Phase detector architecture for phase error estimating and zero phase restarting

by STASZEWSKI ROBERT B, SPAGNA FULVIO
Year of Publication 01.07.2003

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Patent

Phase detector architecture for phase error estimating and zero phase restarting

Phase detector architecture for phase error estimating and zero phase restarting

by Staszewski, Robert B, Spagna, Fulvio
Year of Publication 01.07.2003

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Patent

High performance interconnect physical layer

High performance interconnect physical layer

by SHARMA DEBENDRA DAS, JUE DARREN S, SWANSON JEFFREY C, BLANKENSHIP ROBERT G, IYER VENKATRAMAN, SPAGNA FULVIO
Year of Publication 29.08.2017

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Patent

DELAY LOCKED LOOP FOR TIMING RECOVERY AND WRITE PRECOMPENSATION FOR A READ CHANNEL OF A MASS DATA STORAGE DEVICE, OR THE LIKE

DELAY LOCKED LOOP FOR TIMING RECOVERY AND WRITE PRECOMPENSATION FOR A READ CHANNEL OF A MASS DATA STORAGE DEVICE, OR THE LIKE

by CHEN SHIN CHUNG, SPAGNA FULVIO
Year of Publication 03.01.2002

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Patent

DELAY LOCKED LOOP FOR TIMING RECOVERY AND WRITE PRECOMPENSATION FOR A READ CHANNEL OF A MASS DATA STORAGE DEVICE, OR THE LIKE

DELAY LOCKED LOOP FOR TIMING RECOVERY AND WRITE PRECOMPENSATION FOR A READ CHANNEL OF A MASS DATA STORAGE DEVICE, OR THE LIKE

by SPAGNA, FULVIO, CHEN, SHIN CHUNG
Year of Publication 03.01.2002

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Patent

An improved delay compensation technique for digital clock recovery loops

An improved delay compensation technique for digital clock recovery loops

by Spagna, F.
Published in ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) (2001)

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Conference Proceeding

High performance interconnect physical layer

High performance interconnect physical layer

by GUPTA ASHISH, JUE DARREN S, BLANKENSHIP ROBERT G, IYER VENKATRAMAN, SPAGNA FULVIO
Year of Publication 31.05.2017

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Patent

Open-loop voltage regulation and drift compensation for digitally controlled oscillator (DCO)

Open-loop voltage regulation and drift compensation for digitally controlled oscillator (DCO)

by TONG GULUKE, GOWDER SUJATHA B, LI SHENGGAO, SPAGNA FULVIO
Year of Publication 10.05.2017

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Patent

Simple glitchless phase selection method for multiplexing the phase interpolated clocks

Simple glitchless phase selection method for multiplexing the phase interpolated clocks

by CHEN SHIN CHUNG, SPAGNA FULVIO
Year of Publication 03.07.2001

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Patent

A 90nm 1-4.25-Gb/s Multi Data Rate Receiver for High Speed Serial Links

A 90nm 1-4.25-Gb/s Multi Data Rate Receiver for High Speed Serial Links

by Lidong Chen, Spagna, F., Marzolf, P., Wu, J.K.
Published in 2006 IEEE Asian Solid-State Circuits Conference (01.11.2006)

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Conference Proceeding

HIGH PERFORMANCE INTERCONNECT

HIGH PERFORMANCE INTERCONNECT

by SAFRANEK ROBERT J, FAHIM BAHAA, DAS ABHISHEK, HUM HERBERT H, IYER SITARAMAN V, GUPTA ASHISH, JUE DARREN S, SPINK AARON T, SWANSON JEFFREY C, BLANKENSHIP ROBERT G, JOHNSON SIMON P, LIU YENNG, GEETHA VEDARAMAN, SPAGNA FULVIO, NALE BILL HARRY, SHAH RAHUL C, MADDOX ROBERT A, DAS SHARMA DEBENDRA, WILLEY JEFF, RAMANUJAN RAJ K, KUMAR ARVIND A, BEERS ROBERT, DHILLON YUVRAJ S, IYER VENKATRAMAN
Year of Publication 24.04.2014

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Patent

Hochleistungsverdrahtungs-Bitübertragungsschicht

Hochleistungsverdrahtungs-Bitübertragungsschicht

by SWANSON, JEFFREY C, JUE, DARREN S, SPAGNA, FULVIO, DAS SHARMA, DEBENDRA, BLANKENSHIP, ROBERT G, IYER, VENKATRAMAN
Year of Publication 02.07.2015

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Patent

Hochleistungsfähige physikalische Kopplungsstrukturschicht

Hochleistungsfähige physikalische Kopplungsstrukturschicht

by JUE, DARREN S, GUPTA, ASHISH, SPAGNA, FULVIO, BLANKENSHIP, ROBERT G, IYER, VENKATRAMAN
Year of Publication 16.04.2015

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Patent

HIGH RESOLUTION WIDE RANGE WRITE PRECOMPENSATION

HIGH RESOLUTION WIDE RANGE WRITE PRECOMPENSATION

by KNUTSON JACK R, ROSKY DAVID S, SPAGNA FULVIO
Year of Publication 07.02.2002

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Patent

HIGH RESOLUTION WIDE RANGE WRITE PRECOMPENSATION

HIGH RESOLUTION WIDE RANGE WRITE PRECOMPENSATION

by SPAGNA, FULVIO, ROSKY, DAVID S, KNUTSON, JACK R
Year of Publication 07.02.2002

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Patent

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