A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS
Pellerano, S., Palaskas, Y., Soumyanath, K.
Published in IEEE journal of solid-state circuits (01.07.2008)
Published in IEEE journal of solid-state circuits (01.07.2008)
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Journal Article
A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS
Walling, J.S., Lakdawala, H., Palaskas, Y., Ravi, A., Degani, O., Soumyanath, K., Allstot, D.J.
Published in IEEE journal of solid-state circuits (01.06.2009)
Published in IEEE journal of solid-state circuits (01.06.2009)
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Journal Article
A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion
Elmala, M., Paramesh, J., Soumyanath, K.
Published in IEEE journal of solid-state circuits (01.06.2006)
Published in IEEE journal of solid-state circuits (01.06.2006)
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Journal Article
A highly linear 25dBm outphasing power amplifier in 32nm CMOS for WLAN application
Hongtao Xu, Palaskas, Yorgos, Ravi, Ashoke, Soumyanath, Krishnamurthy
Published in 2010 Proceedings of ESSCIRC (01.09.2010)
Published in 2010 Proceedings of ESSCIRC (01.09.2010)
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Conference Proceeding
A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application: SPECIAL ISSUE ON THE 36th EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (ESSCIRC)
HONGTAO XU, PALASKAS, Yorgos, RAVI, Ashoke, SAJADIEH, Masoud, EL-TANANI, Mohammed A, SOUMYANATH, Krishnamurthy
Published in IEEE journal of solid-state circuits (2011)
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Published in IEEE journal of solid-state circuits (2011)
Journal Article
A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver
Lakdawala, H., Schaecher, M., Fu, C., Limaye, R., Duster, J., Tan, Y., Balankutty, A., Alpman, E., Lee, C. C., Nguyen, K. M., Lee, H., Ravi, A., Suzuki, S., Carlton, B. R., Kim, H. S., Verhelst, M., Pellerano, S., Kim, T., Venkatesan, S., Srivastava, D., Vandervoorn, P., Rizk, J., Jan, C., Ramamurthy, S., Yavatkar, R., Soumyanath, K.
Published in IEEE journal of solid-state circuits (01.01.2013)
Published in IEEE journal of solid-state circuits (01.01.2013)
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Journal Article
Conference Proceeding
Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/T/ CMOS process
Hazucha, P, Karnik, T, Walstra, S, Bloechel, B A, Tschanz, J W, Maiz, J, Soumyanath, K, Dermer, G E, Narendra, S, De, V, Borkar, S
Published in IEEE journal of solid-state circuits (01.09.2004)
Published in IEEE journal of solid-state circuits (01.09.2004)
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Journal Article
A 1.05 V 1.6 mW, 0.45 ^C 3 \sigma Resolution \Sigma\Delta Based Temperature Sensor With Parasitic Resistance Compensation in 32 nm Digital CMOS Process
Lakdawala, H., Li, Y.W., Raychowdhury, A., Taylor, G., Soumyanath, K.
Published in IEEE journal of solid-state circuits (01.12.2009)
Published in IEEE journal of solid-state circuits (01.12.2009)
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Journal Article
A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS
Li, Y. W., Ornelas, C., Hyung Seok Kim, Lakdawala, H., Ravi, A., Soumyanath, K.
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
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Conference Proceeding
A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS
Musah, T., Sunwoo Kwon, Lakdawala, H., Soumyanath, K., Un-Ku Moon
Published in 2009 IEEE Custom Integrated Circuits Conference (01.09.2009)
Published in 2009 IEEE Custom Integrated Circuits Conference (01.09.2009)
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Conference Proceeding
A 64GHz 6.5 dB NF 15.5 dB gain LNA in 90nm CMOS
Pellerano, S., Palaskas, Y., Soumyanath, K.
Published in ESSCIRC 2007 - 33rd European Solid-State Circuits Conference (01.09.2007)
Published in ESSCIRC 2007 - 33rd European Solid-State Circuits Conference (01.09.2007)
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Conference Proceeding
A 28.6dBm 65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position Modulation
Walling, Jeffrey, Lakdawala, Hasnain, Palaskas, Yorgos, Ravi, Ashoke, Degani, Ofir, Soumyanath, Krishnamurthy, Allstot, David
Published in 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01.02.2008)
Published in 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01.02.2008)
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Conference Proceeding
32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver
Lakdawala, H., Schaecher, M., Chang-tsung Fu, Limaye, R., Duster, J., Yulin Tan, Balankutty, A., Alpman, E., Chun Lee, Suzuki, S., Carlton, B., Hyung Seok Kim, Verhelst, M., Pellerano, S., Tong Kim, Srivastava, D., Venkatesan, S., Hyung-jin Lee, Vandervoorn, P., Rizk, J., Chia-Hong Jan, Soumyanath, K., Ramamurthy, S.
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
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Conference Proceeding
Measurements and analysis of SER-tolerant latch in a 90-nm Dual-VT CMOS process
HAZUCHA, Peter, KARNIK, Tanay, BORKAR, Shekhar, WALSTRA, Steven, BLOECHEL, Bradley A, TSCHANZ, James W, MAIZ, Jose, SOUMYANATH, Krishnamurthy, DERMER, Gregory E, NARENDRA, Siva, DE, Vivek
Published in IEEE journal of solid-state circuits (01.09.2004)
Published in IEEE journal of solid-state circuits (01.09.2004)
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Journal Article