Total Performance of 32-nm-Node Ultralow- k /Cu Dual-Damascene Interconnects Featuring Short-TAT Silylated Porous Silica (k = \hbox)
Oda, N, Chikaki, S, Kubota, T, Nakao, S, Tomioka, K, Soda, E, Nakamura, N, Gawase, A, Nogawa, J, Kawashima, Y, Hayashi, R, Suzuki, T, Saito, S
Published in IEEE transactions on electron devices (01.11.2010)
Published in IEEE transactions on electron devices (01.11.2010)
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Fabrication of 70-nm-Pitch Two-Level Interconnects by using Extreme Ultraviolet Lithography
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Published in Japanese Journal of Applied Physics (01.02.2011)
Published in Japanese Journal of Applied Physics (01.02.2011)
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Etch-Byproduct Pore Sealing for Atomic-Layer-Deposited-TaN Deposition on Porous Low-k Film
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Published in Japanese Journal of Applied Physics (01.10.2005)
Published in Japanese Journal of Applied Physics (01.10.2005)
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Fabrication of 70-nm-Pitch Two-Level Interconnects by using Extreme Ultraviolet Lithography
Nakamura, Naofumi, Oda, Noriaki, Soda, Eiichi, Aoyama, Hajime, Tanaka, Yuusuke, Kawamura, Daisuke, Hosoi, Nobuki, Takigawa, Yukio, Shiohara, Morio, Kondo, Seiichi, Mori, Ichiro, Saito, Shuichi
Published in Japanese Journal of Applied Physics (01.02.2011)
Published in Japanese Journal of Applied Physics (01.02.2011)
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Specific oxygen-binding to a polymer-supported N, N-disalicylidenethylenediaminocobalt complex
Nishide, Hiroyuki, Soda, Eiichi, Mizuma, Hiroyuki, Tsuchida, Eishun
Published in Macromolecular symposia. (01.03.1996)
Published in Macromolecular symposia. (01.03.1996)
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Novel Air-gap Formation Technology Using Ru Barrier Metal for Cu Interconnects with High Reliability and Low Capacitance
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Published in Japanese Journal of Applied Physics (01.01.2011)
Published in Japanese Journal of Applied Physics (01.01.2011)
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STRAINER DEVICE
SHIRAIWA KYOJI, MATSUMOTO KAZUFUMI, KATO SHUICHI, SODA EIICHI, ABE KYOICHI, KIMIGAKI NOBUYUKI, FUJII MINORU, IRIE YUKIO
Year of Publication 15.06.2017
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Year of Publication 15.06.2017
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Ultralow-k/Cu Damascene Multilevel Interconnects Using High Porosity and High Modulus Self-Assembled Porous Silica
Chikaki, Shinichi, Kinoshita, Keizo, Kohmura, Kazuo, Tanaka, Hirofumi, Soda, Eiichi, Suzuki, Takamasa, Seino, Yutaka, Hata, Nobuhiro, Saito, Shuichi, Kikkawa, Takamaro
Published in Journal of the Electrochemical Society (2010)
Published in Journal of the Electrochemical Society (2010)
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Total Performance of 32-nm-Node Ultralow-[Formula Omitted]/Cu Dual-Damascene Interconnects Featuring Short-TAT Silylated Porous Silica [Formula Omitted]
Oda, Noriaki, Chikaki, Shinichi, Kubota, Takeo, Nakao, Shinichi, Tomioka, Kazuhiro, Soda, Eiichi, Nakamura, Naofumi, Gawase, Akifumi, Nogawa, Jun, Kawashima, Yoshitsugu, Hayashi, Ryo, Suzuki, Tatsu, Saito, Shuichi
Published in IEEE transactions on electron devices (01.11.2010)
Published in IEEE transactions on electron devices (01.11.2010)
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Trench Sidewall Elimination Effect on Line-to-Line Leakage Current in Scalable Porous Silica ($k= 2.1$)/Cu Interconnect Structure
Gawase, Akifumi, Chikaki, Shinichi, Nakamura, Naofumi, Soda, Eiichi, Oda, Noriaki, Saito, Shuichi
Published in Japanese Journal of Applied Physics (01.05.2010)
Published in Japanese Journal of Applied Physics (01.05.2010)
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