Low-temperature synthesis of high-quality graphene by controlling the carbon-hydrogen ratio of the precursor
Huang, Jian-Zhi, Ni, I-Chih, Hsu, Yun-Hsuan, Li, Shu-Wei, Chan, Yu-Chen, Yang, Shin-Yi, Lee, Ming-Han, Shue, Shau-Lin, Chen, Mei-Hsin, Wu, Chih-I
Published in Nano express (01.03.2022)
Published in Nano express (01.03.2022)
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Journal Article
Improving the Electromigration Life of Advanced Interconnects through Graphene Capping
Huang, Jian-Zhi, Tsao, Po-Chou, Chang, En-Cheng, Jiang, Zih-Kang, Ni, I-Chih, Li, Shu-Wei, Chan, Yu-Chen, Yang, Shin-Yi, Lee, Ming-Han, Shue, Shau-Lin, Chen, Mei-Hsin, Wu, Chih-I
Published in ACS applied nano materials (14.07.2023)
Published in ACS applied nano materials (14.07.2023)
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Journal Article
Intercalated Multilayer Graphene with Ultra Low Resistance for Next-Generation Interconnects
Huang, Jian-Zhi, Chang, En-Cheng, Tsao, Po-Chou, Ni, I-Chih, Li, Shu-Wei, Chan, Yu-Chen, Yang, Shin-Yi, Lee, Ming-Han, Shue, Shau-Lin, Chen, Mei-Hsin, Wu, Chih-I
Published in ACS applied nano materials (23.06.2023)
Published in ACS applied nano materials (23.06.2023)
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Journal Article
Ultra-thin ALD-MnN barrier for low resistance advanced interconnect technology
Shin-Yi Yang, Ming-Han Lee, Ching-Fu Yeh, Shih-Kang Fu, Yu-Chen Chan, Shau-Lin Shue, Min Cao
Published in 2017 IEEE International Interconnect Technology Conference (IITC) (01.05.2017)
Published in 2017 IEEE International Interconnect Technology Conference (IITC) (01.05.2017)
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Conference Proceeding
Low-via-resistance and low-cost PVD-TiZrN barrier for Cu/low-K interconnects
Chan, Yu-Chen, Peng, Chao-Hsien, Lee, Ming-Han, Yang, Shin-Yi, Yeh, Ching-Fu, Shue, Shau-Lin
Published in 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC) (01.05.2016)
Published in 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC) (01.05.2016)
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Conference Proceeding
Journal Article
USING A SELF-ASSEMBLY LAYER TO FACILITATE SELECTIVE FORMATION OF AN ETCHING STOP LAYER
HUANG HSIN YEN, CHEN HAI CHING, LEE CHENG CHIN, LEE SHAO KUAN, WU YUNG HSU, SHUE SHAU LIN
Year of Publication 12.08.2021
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Year of Publication 12.08.2021
Patent
INTEGRATED CHIP WITH CAVITY STRUCTURE
LIAO WEI HAO, LU ZHI WEI, YAO XIN JIE, DAI YU TENG, LI ZHONG RU, TIAN XI WEN, SHUE SHAU-LIN
Year of Publication 21.01.2022
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Year of Publication 21.01.2022
Patent
USING A SELF-ASSEMBLY LAYER TO FACILITATE SELECTIVE FORMATION OF AN ETCHING STOP LAYER
HUANG HSIN YEN, CHEN HAI CHING, LEE CHENG CHIN, LEE SHAO KUAN, WU YUNG HSU, SHUE SHAU LIN
Year of Publication 06.01.2020
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Year of Publication 06.01.2020
Patent
INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF
LEE HSIANG HUAN, YANG SHIN YI, LEE MING HAN, TIEN HSI WEN, SHUE SHAU LIN
Year of Publication 02.10.2015
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Year of Publication 02.10.2015
Patent
AN INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME
TSAI CHENG HSIUNG, CHEN HAI CHING, LEE CHUNG JU, BAO TIEN I, SHUE SHAU LIN
Year of Publication 08.07.2015
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Year of Publication 08.07.2015
Patent
METHOD FOR INTERCONNECT SCHEME
TSAI CHENG HSIUNG, LEE CHUNG JU, YAO HSIN CHIEH, BAO TIEN I, TIEN HSI WEN, WU YUNG HSU, HUANG CHIEN HUA, SHUE SHAU LIN, DIAZ CARLOS H
Year of Publication 01.02.2017
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Year of Publication 01.02.2017
Patent
METHOD FOR INTEGRATED CIRCUIT PATTERNING
WU CHIEH HAN, TSAI CHENG HSIUNG, LIU RU GUN, LEE CHUNG JU, SHIEH MING FENG, BAO TIEN I, SHUE SHAU LIN
Year of Publication 29.06.2015
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Year of Publication 29.06.2015
Patent
SELF-ALIGNED DOUBLE SPACER PATTERNING PROCESS
HUANG TSUNG MIN, TSAI CHENG HSIUNG, LEE CHUNG JU, BAO TIEN I, WU YUNG HSU, SHUE SHAU LIN
Year of Publication 15.06.2015
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Year of Publication 15.06.2015
Patent
METHOD FOR INTEGRATED CIRCUIT PATTERNING
LIU RU GUN, LEE CHUNG JU, SHIEH MING FENG, BAO TIEN I, HSIEH HUNG CHANG, SHUE SHAU LIN
Year of Publication 11.03.2015
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Year of Publication 11.03.2015
Patent