Evolution of Cu Electro-Deposition Technologies for 45nm and Beyond
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Conference Proceeding
Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking
Chen, D.Y., Chiou, W.C., Chen, M.F., Wang, T.D., Ching, K.M., Tu, H.J., Wu, W.J., Yu, C.L., Yang, K.F., Chang, H.B., Tseng, M.H., Hsiao, C.W., Lu, Y.J., Hu, H.P., Lin, Y.C., Hsu, C.S., Shue, W.S., Yu, C.H.
Published in 2009 IEEE International Electron Devices Meeting (IEDM) (01.12.2009)
Published in 2009 IEEE International Electron Devices Meeting (IEDM) (01.12.2009)
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A 90 nm generation copper dual damascene technology with ALD TaN barrier
Peng, C.H., Hsieh, C.H., Huang, C.L., Lin, J.C., Tsai, M.H., Lin, M.W., Chang, C.L., Shue, W.S., Liang, M.S.
Published in Digest. International Electron Devices Meeting (2002)
Published in Digest. International Electron Devices Meeting (2002)
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High performance/reliability Cu interconnect with selective CoWP cap
Ko, T., Chang, C.L., Chou, S.W., Lin, M.W., Lin, C.J., Shih, C.H., Su, H.W., Tsai, M.H., Shue, W.S., Liang, M.S.
Published in 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) (2003)
Published in 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) (2003)
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Effect of Cu Line Capping Process on Stress Migration Reliability
Yhe, M.-S., Chang, H.I., Shih, C.H., Lin, C.J., Ko, T., Su, H.W., Chen, C.H., Tsai, M.H., Shue, W.S., Yu, C.H., Liang, S.M.
Published in 2006 International Interconnect Technology Conference (2006)
Published in 2006 International Interconnect Technology Conference (2006)
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CMP-free and CMP-less approaches for multilevel Cu/low-k BEOL integration
Tsai, M.H., Chou, S.W., Chang, C.L., Hsieha, C.H., Lin, M.W., Wu, C.M., Shue, W.S., Yu, D.C., Liang, M.S.
Published in International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) (2001)
Published in International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) (2001)
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Conference Proceeding
Design of ECP additive for 65 nm-node technology Cu BEOL reliability
Shih, C.H., Chou, S.W., Lin, C.J., Ko, T., Su, H.W., Wu, C.M., Tsai, M.H., Shue, W.S., Yu, C.H., Liang, M.S.
Published in Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005 (2005)
Published in Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005 (2005)
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High performance Cu interconnects capped with full-coverage ALD TaNx layer for Cu/low-k (k/spl sim/2.5) metallization
Hsien-Ming Lee, Lin, J.C., Peng, C.H., Pan, S.C., Huang, C.L., Su, L.L., Hsieh, C.H., Shue, W.S., LIang, M.S.
Published in Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729) (2004)
Published in Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729) (2004)
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