A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier
Jo, Yongwoo, Kim, Juyeop, Shin, Yuhwan, Park, Hangi, Hwang, Chanwoong, Lim, Younghyun, Choi, Jaehyouk
Published in IEEE journal of solid-state circuits (01.12.2023)
Published in IEEE journal of solid-state circuits (01.12.2023)
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Journal Article
A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces
Shin, Yuhwan, Jo, Yongwoo, Kim, Juyeop, Lee, Junseok, Kim, Jongwha, Choi, Jaehyouk
Published in IEEE journal of solid-state circuits (01.08.2024)
Published in IEEE journal of solid-state circuits (01.08.2024)
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Journal Article
10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique
Shin, Yuhwan, Lee, Junseok, Kim, Juyeop, Jo, Yongwoo, Choi, Jaehyouk
Published in 2024 IEEE International Solid-State Circuits Conference (ISSCC) (18.02.2024)
Published in 2024 IEEE International Solid-State Circuits Conference (ISSCC) (18.02.2024)
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Conference Proceeding
A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator
Park, Suneui, Yoo, Seyeon, Shin, Yuhwan, Lee, Jeonghyun, Choi, Jaehyouk
Published in 2022 IEEE International Solid- State Circuits Conference (ISSCC) (20.02.2022)
Published in 2022 IEEE International Solid- State Circuits Conference (ISSCC) (20.02.2022)
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Conference Proceeding
A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier
Jo, Yongwoo, Kim, Juyeop, Shin, Yuhwan, Hwang, Chanwoong, Park, Hangi, Choi, Jaehyouk
Published in 2023 IEEE International Solid- State Circuits Conference (ISSCC) (19.02.2023)
Published in 2023 IEEE International Solid- State Circuits Conference (ISSCC) (19.02.2023)
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Conference Proceeding
28.5 A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces
Shin, Yuhwan, Jo, Yongwoo, Kim, Juyeop, Lee, Junseok, Kim, Jongwha, Choi, Jaehyouk
Published in 2023 IEEE International Solid- State Circuits Conference (ISSCC) (19.02.2023)
Published in 2023 IEEE International Solid- State Circuits Conference (ISSCC) (19.02.2023)
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Conference Proceeding