The Next Generation 64b SPARC Core in a T4 SoC Processor
Shin, Jinuk Luke, Golla, Robert, Li, Hongping, Dash, Sudesna, Choi, Youngmoon, Smith, Alan, Sathianathan, Harikaran, Joshi, Mayur, Park, Heechoul, Elgebaly, Mohamed, Turullols, Sebastian, Kim, Song, Masleid, Robert, Konstadinidis, Georgios K., Doherty, Mary Jo, Grohoski, Greg, McAllister, Curtis
Published in IEEE journal of solid-state circuits (01.01.2013)
Published in IEEE journal of solid-state circuits (01.01.2013)
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Conference Proceeding
AI SoC Design Challenges in the Foundation Model Era
Chen, Zhengyu, Huang, Dawei, Wang, Mingran, Yang, Bowen, Shin, Jinuk Luke, Hu, Changran, Li, Bo, Prabhakar, Raghu, Deng, Gao, Sheng, Yongning, Fu, Sihua, Yuan, Lu, Zhao, Tian, Du, Yun, Liu, Chen, Yang, Jun, Shah, Viren, Srinivasan, Venkat, Jairath, Sumti
Published in 2023 IEEE Custom Integrated Circuits Conference (CICC) (01.04.2023)
Published in 2023 IEEE Custom Integrated Circuits Conference (CICC) (01.04.2023)
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Conference Proceeding
A Power-Efficient High-Throughput 32-Thread SPARC Processor
Leon, A.S., Tam, K.W., Shin, J.L., Weisner, D., Schumacher, F.
Published in IEEE journal of solid-state circuits (01.01.2007)
Published in IEEE journal of solid-state circuits (01.01.2007)
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A 40 nm 16-Core 128-Thread SPARC SoC Processor
Shin, Jinuk Luke, Huang, Dawei, Petrick, Bruce, Hwang, Changku, Tam, Kenway W., Smith, Alan, Pham, Ha, Li, Hongping, Johnson, Timothy, Schumacher, Francis, Leon, Ana Sonia, Strong, Allan
Published in IEEE journal of solid-state circuits (01.01.2011)
Published in IEEE journal of solid-state circuits (01.01.2011)
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A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm
Hart, Jason M., Hoyeol Cho, Yuefei Ge, Gruber, Gregory, Dawei Huang, Changku Hwang, Jian, Daisy, Johnson, Tim, Konstadinidis, Georgios K., Krishnaswamy, Venkat, Kwong, Lance, Masleid, Robert P., Mehta, Rakesh, Nawathe, Umesh, Ramachandran, Aparna, Sathianathan, Hari, Yongning Sheng, Shin, Jinuk Luke, Turullols, Sebastian, Zuxu Qin, Yen, King C.
Published in IEEE journal of solid-state circuits (01.01.2014)
Published in IEEE journal of solid-state circuits (01.01.2014)
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Journal Article
A 40nm 16-core 128-thread CMT SPARC SoC processor
Shin, Jinuk Luke, Tam, Kenway, Huang, Dawei, Petrick, Bruce, Pham, Ha, Hwang, Changku, Li, Hongping, Smith, Alan, Johnson, Timothy, Schumacher, Francis, Greenhill, David, Leon, Ana Sonia, Strong, Allan
Published in 2010 IEEE International Solid-State Circuits Conference - (ISSCC) (01.02.2010)
Published in 2010 IEEE International Solid-State Circuits Conference - (ISSCC) (01.02.2010)
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Conference Proceeding
4.3 Fine-grained adaptive power management of the SPARC M7 processor
Krishnaswamy, Venkat, Brooks, Jeffrey, Konstadinidis, Georgios, McAllister, Curtis, Pham, Ha, Turullols, Sebastian, Shin, Jinuk Luke, Yifan YangGong, Haowei Zhang
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
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Conference Proceeding
Journal Article
The UltraSPARC T1 Processor: CMT Reliability
Leon, A.S., Langley, B., Jinuk Luke Shin
Published in IEEE Custom Integrated Circuits Conference 2006 (01.09.2006)
Published in IEEE Custom Integrated Circuits Conference 2006 (01.09.2006)
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Conference Proceeding
A dual-core 64-bit ultraSPARC microprocessor for dense server applications
Takayanagi, T., Shin, J.L., Petrick, B., Su, J.Y., Levy, H., Ha Pham, Son, J., Moon, N., Bistry, D., Nair, U., Singh, M., Mathur, V., Leon, A.S.
Published in IEEE journal of solid-state circuits (01.01.2005)
Published in IEEE journal of solid-state circuits (01.01.2005)
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Conference Proceeding
SambaNova SN10 RDU: A 7nm Dataflow Architecture to Accelerate Software 2.0
Prabhakar, Raghu, Jairath, Sumti, Shin, Jinuk Luke
Published in 2022 IEEE International Solid- State Circuits Conference (ISSCC) (20.02.2022)
Published in 2022 IEEE International Solid- State Circuits Conference (ISSCC) (20.02.2022)
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Conference Proceeding
Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor
Yifan YangGong, Turullols, Sebastian, Woo, Daniel, Changku Huang, King Yen, Krishnaswamy, Venkat, Holdbrook, Kalon, Shin, Jinuk Luke
Published in 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) (01.11.2014)
Published in 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) (01.11.2014)
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Conference Proceeding
A dual-core 64b ultraSPARC microprocessor for dense server applications
Takayanagi, Toshinari, Shin, Jinuk Luke, Petrick, Bruce, Su, Jeffrey, Leon, Ana Sonia
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004 (07.06.2004)
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004 (07.06.2004)
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Conference Proceeding
Bandwidth and power management of glueless 8-socket SPARC T5 system
Krishnaswamy, V., Dawei Huang, Turullols, S., Shin, J. L.
Published in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (01.02.2013)
Published in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (01.02.2013)
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Conference Proceeding
Design and implementation of an embedded 512-KB level-2 cache subsystem
Shin, J.L., Petrick, B., Singh, M., Leon, A.S.
Published in IEEE journal of solid-state circuits (01.09.2005)
Published in IEEE journal of solid-state circuits (01.09.2005)
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Conference Proceeding
4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor
Li, Penny, Shin, Jinuk Luke, Konstadinidis, Georgios, Schumacher, Francis, Krishnaswamy, Venkat, Hoyeol Cho, Dash, Sudesna, Masleid, Robert, Chaoyang Zheng, Lin, Yuanjung David, Loewenstein, Paul, Heechoul Park, Srinivasan, Vijay, Dawei Huang, Changku Hwang, Hsu, Wenjay, McAllister, Curtis
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
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Conference Proceeding
Journal Article
The next-generation 64b SPARC core in a T4 SoC processor
Shin, Jinuk Luke, Heechoul Park, Hongping Li, Smith, A., Youngmoon Choi, Sathianathan, H., Dash, S., Turullols, S., Song Kim, Masleid, R., Konstadinidis, G., Golla, R., Doherty, M. J., Grohoski, G., McAllister, C.
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
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Conference Proceeding
3.6GHz 16-core SPARC SoC processor in 28nm
Hart, J., Butler, S., Hoyeol Cho, Yuefei Ge, Gruber, G., Dawei Huang, Changku Hwang, Jian, D., Johnson, T., Konstadinidis, G., Kwong, L., Masleid, R., Nawathe, U., Ramachandran, A., Yongning Sheng, Shin, J. L., Turullois, S., Zuxu Qin, King Yen
Published in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (01.02.2013)
Published in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (01.02.2013)
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Conference Proceeding
Session 4 overview: Processors: High-performance digital subcommittee
Inoue, Atsuki, Shin, Jinuk Luke
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
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Journal Article
Design and implementation of an embedded 512KB level 2 cache subsystem
Jinuk Luke Shin, Petrick, B., Levy, H., Jinseung Son, Mandeep Singh, Mathur, V., Jung-Cheng Yeh, Heesung Choi, Gupta, V., Ziaja, T., Leon, A.S.
Published in Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) (2004)
Published in Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) (2004)
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Conference Proceeding