Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register
Idei, Y., Shimohigashi, K., Aoki, M., Noda, H., Iwai, H., Sato, K., Tachibana, T.
Published in IEEE journal of solid-state circuits (01.02.1998)
Published in IEEE journal of solid-state circuits (01.02.1998)
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Journal Article
Design and performance of 0.1- mu m CMOS devices using low-impurity-channel transistors (LICT's)
Aoki, M., Ishii, T., Yoshimura, T., Kiyota, Y., Iijima, S., Yamanaka, T., Kure, T., Ohyu, K., Nishida, T., Okazaki, S., Seki, K., Shimohigashi, K.
Published in IEEE electron device letters (01.01.1992)
Published in IEEE electron device letters (01.01.1992)
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Journal Article
An alpha -immune, 2-V supply voltage SRAM using a polysilicon PMOS load cell
Ishibashi, K., Yamanaka, T., Shimohigashi, K.
Published in IEEE journal of solid-state circuits (01.02.1990)
Published in IEEE journal of solid-state circuits (01.02.1990)
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Journal Article
A high-current-gain low-temperature pseudo-HBT utilizing a sidewall base-contact structure (SICOS)
Yano, K., Nakazato, K., Miyamoto, M., Aoki, M., Shimohigashi, K.
Published in IEEE electron device letters (01.10.1989)
Published in IEEE electron device letters (01.10.1989)
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Journal Article
Base-emitter injection characterization in low-temperature pseudo-heterojunction bipolar transistors
Yano, K., Nakazato, K., Miyamoto, M., Aoki, M., Shimohigashi, K.
Published in IEEE transactions on electron devices (01.10.1990)
Published in IEEE transactions on electron devices (01.10.1990)
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Journal Article
Quasi-complementary BiCMOS for sub-3-V digital circuits
Yano, K., Hiraki, M., Shukuri, S., Onose, Y., Hirao, M., Ohki, N., Nishida, T., Seki, K., Shimohigashi, K.
Published in IEEE journal of solid-state circuits (01.11.1991)
Published in IEEE journal of solid-state circuits (01.11.1991)
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Journal Article
A 9-ns 1-Mbit CMOS SRAM
Sasaki, K., Ishibashi, K., Yamanaka, T., Hashimoto, N., Nishida, T., Shimohigashi, K., Hanamura, S., Honjo, S.
Published in IEEE journal of solid-state circuits (01.10.1989)
Published in IEEE journal of solid-state circuits (01.10.1989)
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Journal Article
An experimental large-capacity semiconductor file memory using 16-levels/cell storage
Horiguchi, M., Aoki, M., Nakagome, Y., Ikenaga, S., Shimohigashi, K.
Published in IEEE journal of solid-state circuits (01.02.1988)
Published in IEEE journal of solid-state circuits (01.02.1988)
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Journal Article
A 23-ns 4-Mb CMOS SRAM with 0.2- mu A standby current
Sasaki, K., Ishibashi, K., Shimohigashi, K., Yamanaka, T., Moriwake, N., Honjo, S., Ikeda, S., Koike, A., Meguro, S., Minato, O.
Published in IEEE journal of solid-state circuits (01.10.1990)
Published in IEEE journal of solid-state circuits (01.10.1990)
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Journal Article
Fully symmetric cooled CMOS on (110) plane
AOKI, M, YANO, K, MASUHARA, T, SHIMOHIGASHI, K
Published in IEEE transactions on electron devices (01.08.1989)
Published in IEEE transactions on electron devices (01.08.1989)
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Journal Article
Alpha-particle-induced charge collection measurements for megabit DRAM cells
Takeuchi, K., Shimohigashi, K., Takeda, E., Yamasaki, E., Toyabe, T., Itoh, K.
Published in IEEE transactions on electron devices (01.09.1989)
Published in IEEE transactions on electron devices (01.09.1989)
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Journal Article
High-frequency characteristics of low-temperature pseudo-heterojunction bipolar transistors
Miyamoto, M., Yano, K., Tamaki, Y., Aoki, M., Nishida, T., Seki, K., Shimohigashi, K.
Published in IEEE transactions on electron devices (01.02.1993)
Published in IEEE transactions on electron devices (01.02.1993)
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Journal Article
Origin and characteristics of alpha-particle-induced permanent junction leakage
Takeuchi, K., Shimohigashi, K., Kozuka, H., Toyabe, T., Itoh, K., Kurosawa, H.
Published in IEEE transactions on electron devices (01.03.1990)
Published in IEEE transactions on electron devices (01.03.1990)
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Journal Article
A feedback-type BiCMOS logic gate
Nishio, Y., Murabayashi, F., Kotoku, S., Watnabe, A., Shukuri, S., Shimohigashi, K.
Published in IEEE journal of solid-state circuits (01.10.1989)
Published in IEEE journal of solid-state circuits (01.10.1989)
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Journal Article
A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM
Suzuki, M., Tachibana, S., Watanabe, A., Shukuri, S., Higuchi, H., Nagano, T., Shimohigashi, K.
Published in IEEE journal of solid-state circuits (01.10.1989)
Published in IEEE journal of solid-state circuits (01.10.1989)
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Journal Article
A 16-level/cell dynamic memory
Aoki, M., Nakagome, Y., Horiguchi, M., Ikenaga, S., Shimohigashi, K.
Published in IEEE journal of solid-state circuits (01.04.1987)
Published in IEEE journal of solid-state circuits (01.04.1987)
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Journal Article
Short-channel MOSFET's in the punchthrough current mode
Barnes, J.J., Shimohigashi, K., Dutton, R.W.
Published in IEEE transactions on electron devices (01.04.1979)
Published in IEEE transactions on electron devices (01.04.1979)
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Journal Article