Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs With MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs
Lee, Shen-Yang, Chen, Han-Wei, Shen, Chiuan-Huei, Kuo, Po-Yi, Chung, Chun-Chih, Huang, Yu-En, Chen, Hsin-Yu, Chao, Tien-Sheng
Published in IEEE transactions on electron devices (01.02.2020)
Published in IEEE transactions on electron devices (01.02.2020)
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Journal Article
Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process
Lee, Shen-Yang, Chen, Han-Wei, Shen, Chiuan-Huei, Kuo, Po-Yi, Chung, Chun-Chih, Huang, Yu-En, Chen, Hsin-Yu, Chao, Tien-Sheng
Published in IEEE electron device letters (01.11.2019)
Published in IEEE electron device letters (01.11.2019)
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Journal Article
Stacked Sidewall-Damascene Double-Layer Poly-Si Trigate FETs With RTA-Improved Crystallinity
Shen, Chiuan-Huei, Kuo, Po-Yi, Chung, Chun-Chih, Lee, Sen-Yang, Chao, Tien-Sheng
Published in IEEE electron device letters (01.04.2018)
Published in IEEE electron device letters (01.04.2018)
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Journal Article
Variable-Channel Junctionless Poly-Si FETs: Demonstration and Investigation With Different Body Doping Concentrations
Lin, Jer-Yi, Tsai, Chan-Yi, Shen, Chiuan-Huei, Chung, Chun-Chih, Kumar, Malkundi Puttaveerappa Vijay, Chao, Tien-Sheng
Published in IEEE electron device letters (01.09.2018)
Published in IEEE electron device letters (01.09.2018)
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Journal Article
Investigation of the Impact of Internal Metal Gate - From MFM Capacitors to Two-Layer-Stacked GAA Poly-Si NW FE-FETs
Lee, Shen-Yang, Chen, Han-Wei, Chung, Chun-Chih, Shen, Chiuan-Huei, Kuo, Po-Yi, Huang, Yu-En, Chen, Hsin-Yu, Chao, Tien-Sheng
Published in 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) (01.08.2020)
Published in 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) (01.08.2020)
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Conference Proceeding
Experimental Demonstration of Performance Enhancement of MFMIS and MFIS for 5-nm × 12.5-nm Poly-Si Nanowire Gate-All-Around Negative Capacitance FETs Featuring Seed-Layer and PMA-Free Process
Lee, Shen-Yang, Chen, Han-Wei, Shen, Chiuan-Huei, Kuo, Po-Yi, Chung, Chun-Chih, Huang, Yu-En, Chen, Hsin-Yu, Chao, Tien-Sheng
Published in 2019 Silicon Nanoelectronics Workshop (SNW) (01.06.2019)
Published in 2019 Silicon Nanoelectronics Workshop (SNW) (01.06.2019)
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Conference Proceeding