A Hybrid-PLL (ADPLL/Charge-Pump PLL) Using Phase Realignment With 0.6-us Settling, 0.619-ps Integrated Jitter, and −240.5-dB FoM in 7-nm FinFET
Tsai, Tsung-Hsien, Sheen, Ruey-Bin, Chang, Chih-Hsien, Hsieh, Kenny Cheng-Hsiang, Staszewski, Robert Bogdan
Published in IEEE solid-state circuits letters (2020)
Published in IEEE solid-state circuits letters (2020)
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Journal Article
A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW
Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Staszewski, Robert Bogdan
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
HYBRID PHASE LOCK LOOP
CHANG CHIH HSIEN, HSIEH CHENG HSIANG, SHEEN RUEY BIN, TSAI TSUNG HSIEN
Year of Publication 08.06.2018
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Year of Publication 08.06.2018
Patent
Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS
Chou, Mao-Hsuan, Chang, Ya-Tin, Tsai, Tsung-Hsien, Lu, Tsung-Che, Liao, Chia-Chun, Kuo, Hung-Yi, Sheen, Ruey-Bin, Chang, Chih-Hsien, Hsieh, Kenny C. H., Loke, Alvin L. S., Chen, Mark
Published in 2020 IEEE Symposium on VLSI Circuits (01.06.2020)
Published in 2020 IEEE Symposium on VLSI Circuits (01.06.2020)
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Conference Proceeding
A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur
Tsai, Tsung-Hsien, Sheen, Ruey-Bin, Hsu, Sheng-Yun, Chang, Ya-Tin, Chang, Chih-Hsien, Staszewski, Robert Bogdan
Published in 2022 IEEE International Solid- State Circuits Conference (ISSCC) (20.02.2022)
Published in 2022 IEEE International Solid- State Circuits Conference (ISSCC) (20.02.2022)
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Conference Proceeding
A low-power adder operating on effective dynamic data ranges
Chen, O.T.-C., Sheen, R.R.-B., Wang, S.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.08.2002)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.08.2002)
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Journal Article