A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme
Chun, Ki Chul, Kim, Yong Ki, Ryu, Yesin, Park, Jaewon, Oh, Chi Sung, Byun, Young Yong, Kim, So Young, Shin, Dong Hak, Lee, Jun Gyu, Ho, Byung-Kyu, Park, Min-Sang, Cho, Seong-Jin, Woo, Seunghan, Moon, Byoung Mo, Kil, Beomyong, Ahn, Sungoh, Lee, Jae Hoon, Kim, Soo Young, Choi, Seouk-Kyu, Jeong, Jae-Seung, Ahn, Sung-Gi, Kim, Jihye, Kong, Jun Jin, Sohn, Kyomin, Kim, Nam Sung, Lee, Jung-Bae
Published in IEEE journal of solid-state circuits (01.01.2021)
Published in IEEE journal of solid-state circuits (01.01.2021)
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Journal Article
An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques
Lee, Chang-Kyo, Chi, Hyung-Joon, Heo, Jin-Seok, Park, Jung-Hwan, Jang, Jin-Hun, Lee, Dongkeon, Jung, Jae-Hoon, Lee, Dong-Hun, Kim, Dae-Hyun, Kim, Kihan, Kim, Sang-Yun, Park, Dukha, Lim, Youngil, Park, Geuntae, Lee, Seung-Jun, Hong, Seungki, Kwon, Dae-Hyun, Hwang, Isak, Na, Byongwook, Kim, Kyung-Ryun, Choi, Seouk-Kyu, Choi, Hyein, Hangi-Jung, Bae, Won-Il, Ihm, Jeong-Don, Bae, Seung-Jun, Kim, Nam Sung, Lee, Jung-Bae
Published in IEEE journal of solid-state circuits (01.01.2021)
Published in IEEE journal of solid-state circuits (01.01.2021)
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Journal Article
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking
Kim, Young-Ju, Kwon, Hye-Jung, Doo, Su-Yeon, Ahn, Minsu, Kim, Yong-Hun, Lee, Yong-Jae, Kang, Dong-Seok, Do, Sung-Geun, Lee, Chang-Yong, Cho, Gun-Hee, Park, Jae-Koo, Kim, Jae-Sung, Park, Kyungbae, Oh, Seunghoon, Lee, Sang-Yong, Yu, Ji-Hak, Yu, Kihun, Jeon, Chulhee, Kim, Sang-Sun, Park, Hyun-Soo, Lee, Jeong-Woo, Cho, Seung-Hyun, Park, Keon-Woo, Kim, Yongjun, Seo, Young-Hun, Shin, Chang-Ho, Lee, Chan-Yong, Bang, Sam-Young, Park, Younsik, Choi, Seouk-Kyu, Kim, Byung-Cheol, Han, Gong-Heum, Bae, Seung-Jun, Kwon, Hyuk-Jun, Choi, Jung-Hwan, Sohn, Young-Soo, Park, Kwang-Il, Jang, Seong-Jin, Jin, Gyoyoung
Published in IEEE journal of solid-state circuits (01.01.2019)
Published in IEEE journal of solid-state circuits (01.01.2019)
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Journal Article
A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process
Kim, Dae-Hyun, Song, Byungkyu, Ahn, Hyun-a, Ko, Woongjoon, Do, Sunggeun, Cho, Seokjin, Kim, Kihan, Oh, Seung-Hoon, Joo, Hye-Yoon, Park, Geuntae, Jang, Jin-Hun, Kim, Yong-Hun, Lee, Donghun, Jung, Jaehoon, Kwon, Yongmin, Kim, Youngjae, Jung, Jaewoo, O, Seongil, Lee, Seoulmin, Lim, Jaeseong, Son, Junho, Min, Jisu, Do, Haebin, Yoon, Jaejun, Hwang, Isak, Park, Jinsol, Shim, Hong, Yoon, Seryeong, Choi, Dongyeong, Lee, Jihoon, Woo, Soohan, Hong, Eunki, Choi, Junha, Kim, Jae-Sung, Han, Sangkeun, Bang, Jongmin, Park, Bokgue, Kim, Janghoo, Choi, Seouk-Kyu, Han, Gong-Heum, Sung, Yoo-Chang, Bae, Won-Il, Lim, Jeong-Don, Lee, Seungjae, Yoo, Changsik, Hwang, Sang Joon, Lee, Jooyoung
Published in 2022 IEEE International Solid-State Circuits Conference (ISSCC) (20.02.2022)
Published in 2022 IEEE International Solid-State Circuits Conference (ISSCC) (20.02.2022)
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Conference Proceeding
23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power
Ha, Kyung-Soo, Lee, Chang-Kyo, Lee, Dongkeon, Moon, Daesik, Jang, Jin-Hun, Hwang, Hyong-Ryol, Chi, Hyungjoon, Park, Junghwan, Shin, Seungjun, Park, Dukha, Kim, Sang-Yun, Lim, Sukhyun, Park, Kiwon, Choi, YeonKyu, Kim, Young-Hwa, Son, Younghoon, Cho, Hyunyoon, Na, Byongwook, Ahn, Hyo-Joo, Lee, Seungseob, Choi, Seouk-Kyu, Park, Youn-Sik, Hyun, Seok-Hun, Chang, Soobong, Kwon, Hyuck-Joon, Choi, Jung-Hwan, Oh, Tae-Young, Sohn, Young-Soo, Park, Kwang-II, Jang, Seong-Jin
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
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Conference Proceeding
22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme
Oh, Chi-Sung, Chun, Ki Chul, Byun, Young-Yong, Kim, Yong-Ki, Kim, So-Young, Ryu, Yesin, Park, Jaewon, Kim, Sinho, Cha, Sanguhn, Shin, Donghak, Lee, Jungyu, Son, Jong-Pil, Ho, Byung-Kyu, Cho, Seong-Jin, Kil, Beomyong, Ahn, Sungoh, Lim, Baekmin, Park, Yongsik, Lee, Kijun, Lee, Myung-Kyu, Baek, Seungduk, Noh, Junyong, Lee, Jae-Wook, Lee, Seungseob, Kim, Sooyoung, Lim, Botak, Choi, Seouk-Kyu, Kim, Jin-Guk, Choi, Hye-In, Kwon, Hyuk-Jun, Kong, Jun Jin, Sohn, Kyomin, Kim, Nam Sung, Park, Kwang-Il, Lee, Jung-Bae
Published in 2020 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2020)
Published in 2020 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2020)
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Conference Proceeding
22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process
Chi, Hyung-Joon, Lee, Chang-Kyo, Park, Junghwan, Heo, Jin-Seok, Jung, Jaehoon, Lee, Dongkeon, Kim, Dae-Hyun, Park, Dukha, Kim, Kihan, Kim, Sang-Yun, Park, Jinsol, Cho, Hyunyoon, Lim, Sukhyun, Choi, YeonKyu, Lim, Youngil, Moon, Daesik, Park, Geuntae, Jang, Jin-Hun, Lee, Kyungho, Hwang, Isak, Kim, Cheol, Son, Younghoon, Kang, Gil-Young, Park, Kiwon, Lee, Seungjun, Doo, Su-Yeon, Shin, Chang-Ho, Na, Byongwook, Kwon, Jisuk, Kim, Kyung Ryun, Choi, Hyein, Choi, Seouk-Kyu, Chang, Soobong, Bae, Wonil, Kwon, Hyuck-Joon, Sohn, Young-Soo, Bae, Seung-Jun, Park, Kwang-Il, Lee, Jung-Bae
Published in 2020 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2020)
Published in 2020 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2020)
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Conference Proceeding
25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM
Kim, Yong-Hun, Kim, Hyung-Jin, Choi, Jaemin, Ahn, Min-Su, Lee, Dongkeon, Cho, Seung-Hyun, Park, Dong-Yeon, Park, Young-Jae, Jang, Min-Soo, Kim, Yong-Jun, Choi, Jinyong, Yoon, Sung-Woo, Jung, Jae-Woo, Park, Jae-Koo, Lee, Jae-Woo, Kwon, Dae-Hyun, Cha, Hyung-Seok, Cho, Si-Hyeong, Kim, Seong-Hoon, You, Jihwa, Kim, Kyoung-Ho, Kim, Dae-Hyun, Kim, Byung-Cheol, Kim, Young-Kwan, Kim, Jun-Ho, Choi, Seouk-Kyu, Kim, Chan-Young, Na, Byong-Wook, Choi, Hye-In, Oh, Reum, Ihm, Jeong-Don, Bae, Seung-Jun, Kim, Nam Sung, Lee, Jung-Bae
Published in 2021 IEEE International Solid- State Circuits Conference (ISSCC) (13.02.2021)
Published in 2021 IEEE International Solid- State Circuits Conference (ISSCC) (13.02.2021)
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Conference Proceeding
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking
Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo, Yoon-Joo Eom, Young-Sik Kim, Min-Su Ahn, Yong-Hun Kim, Sang-Hoon Jung, Sung-Geun Do, Chang-Yong Lee, Jae-Sung Kim, Dong-Seok Kang, Kyung-Bae Park, Jung-Bum Shin, Jong-Ho Lee, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ji-Suk Kwon, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Min-Woo Won, Gun-hee Cho, Hyun-Soo Park, Hyung-Kyu Kim, Jeong-Woo Lee, Seung-Hyun Cho, Keon-Woo Park, Jae-Koo Park, Yong-Jae Lee, YongJun Kim, Young-Hun Seo, Beob-Rae Cho, Chang-Ho Shin, Chan-Yong Lee, YoungSeok Lee, Yoon-Gue Song, Sam-Young Bang, YounSik Park, Seouk-Kyu Choi, Byeong-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
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Conference Proceeding
18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution
Kyomin Sohn, Won-Joo Yun, Reum Oh, Chi-Sung Oh, Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Kyung-Woo Nam, Seouk-Kyu Choi, Jae-Wook Lee, Uksong Kang, Young-Soo Sohn, Jung-Hwan Choi, Chi-Wook Kim, Seong-Jin Jang, Gyo-Young Jin
Published in 2016 IEEE International Solid-State Circuits Conference (ISSCC) (01.01.2016)
Published in 2016 IEEE International Solid-State Circuits Conference (ISSCC) (01.01.2016)
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Conference Proceeding