Search Results - "Sengupta, Rwik" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

A Multi-Bit Neuromorphic Weight Cell Using Ferroelectric FETs, suitable for SoC Integration

A Multi-Bit Neuromorphic Weight Cell Using Ferroelectric FETs, suitable for SoC Integration

by Obradovic, Borna, Rakshit, Titash, Hatcher, Ryan, Kittl, Jorge, Sengupta, Rwik, Hong, Joon Goo, Rodder, Mark S.
Published in IEEE journal of the Electron Devices Society (2018)

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Journal Article

METHOD OF DESIGNING A LAYOUT FOR A SEMICONDUCTOR INTEGRATED CIRCUIT

METHOD OF DESIGNING A LAYOUT FOR A SEMICONDUCTOR INTEGRATED CIRCUIT

by SENGUPTA RWIK, GEROUSIS VASSILIOS
Year of Publication 02.07.2020

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Patent

AN INTEGRATED CIRCUIT APPARATUS AND METHOD OF FORMING A CONDUCTIVE MATERIAL IN A BACKSIDE OF THE INTEGRATED CIRCUIT

AN INTEGRATED CIRCUIT APPARATUS AND METHOD OF FORMING A CONDUCTIVE MATERIAL IN A BACKSIDE OF THE INTEGRATED CIRCUIT

by SENGUPTA RWIK, HONG JOON GOO
Year of Publication 10.09.2020

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Patent

Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICs

Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICs

by Kiran Pentapati, Sai Surya, Chang, Kyungwook, Gerousis, Vassilios, Sengupta, Rwik, Lim, Sung Kyu
Published in 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD) (02.11.2020)

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Conference Proceeding

A Novel Foundry Yield Model Using Critical Area Analysis

A Novel Foundry Yield Model Using Critical Area Analysis

by Qi, Xiaoyuan, Schroeder, Uwe, Sinnott, Aaron, Nair, Binod Kumar G., Sultan, Akif, Madhavan, Sriram, Condella, Jac, Fales, Jonathan, Nelson, Jeffrey, Gennari, Frank, Lai, Ya-Chieh, Sengupta, Rwik, Hurat, Philippe
Published in IEEE transactions on semiconductor manufacturing (01.08.2021)

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Journal Article

VFET STANDARD CELL ARCHITECTURE WITH IMPROVED CONTACT AND SUPER VIA

VFET STANDARD CELL ARCHITECTURE WITH IMPROVED CONTACT AND SUPER VIA

by SENGUPTA RWIK, DO JUNG HO
Year of Publication 24.09.2020

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Patent

LOGIC GATE INTEGRATED CIRCUIT AND DIGITAL CIRCUIT USING UNIPOLAR SEMICONDUCTOR DEVICES

LOGIC GATE INTEGRATED CIRCUIT AND DIGITAL CIRCUIT USING UNIPOLAR SEMICONDUCTOR DEVICES

by HATCHER RYAN M, SENGUPTA RWIK, BOWEN CHRIS
Year of Publication 11.09.2018

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Patent

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

by SENGUPTA RWIK, RODDER MARK STEPHEN, HONG JOON GOO, RAKSHIT TITASH
Year of Publication 20.05.2020

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Patent

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

by GEROUSIS VASSILIOS CONSTANTINOS, SENGUPTA RWIK, HONG JOON GOO, RODDER MARK
Year of Publication 07.05.2020

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Patent

SEMICONDUCTOR CELL BLOCKS HAVING NON-INTEGER MULTIPLE OF CELL HEIGHTS

SEMICONDUCTOR CELL BLOCKS HAVING NON-INTEGER MULTIPLE OF CELL HEIGHTS

by SENGUPTA RWIK, TRAYNOR KEVIN, HONG JOON GOO, RODDER MARK S, ABAYA TANYA, PALLE DHARMENDAR, GEROUSIS VASSILIOS
Year of Publication 31.08.2021

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Patent

SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

by SENGUPTA RWIK, RODDER MARK S
Year of Publication 14.03.2016

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Patent

Semiconductor device and method of fabricating the same and logic microprocessor

Semiconductor device and method of fabricating the same and logic microprocessor

by SENGUPTA RWIK, RAKSHIT TITASH, RODDER MARK
Year of Publication 26.10.2017

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Patent

3T2R 3T2R BINARY WEIGHT CELL WITH HIGH ON/OFF FOR MEMORY DEVICE PROGRAMMED WITH TRANSVERSE CURRENTS

3T2R 3T2R BINARY WEIGHT CELL WITH HIGH ON/OFF FOR MEMORY DEVICE PROGRAMMED WITH TRANSVERSE CURRENTS

by KITTL JORGE, SENGUPTA RWIK, RAKSHIT TITASH, HONG JOON GOO, HATCHER RYAN, PALLE DHARMENDAR
Year of Publication 03.05.2021

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Patent

CELL ARCHITECTURE WITH CONTACT ON ACTIVE GATE COMPATIBLE WITH A SMALL CELL AREA HAVING SMALL CONTACTED POLY PITCH

CELL ARCHITECTURE WITH CONTACT ON ACTIVE GATE COMPATIBLE WITH A SMALL CELL AREA HAVING SMALL CONTACTED POLY PITCH

by SENGUPTA RWIK, HONG JOON GOO, RAKSHIT TITASH, RODDER MARK
Year of Publication 24.05.2019

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Patent

SEMICONDUCTOR DEVICE HAVING BURIED POWER RAIL

SEMICONDUCTOR DEVICE HAVING BURIED POWER RAIL

by SENGUPTA RWIK, HONG, JOON GOO, RODDER MARK
Year of Publication 25.05.2017

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Patent

POWER DISTRIBUTION NETWORK USING BURIED POWER SUPPLY RAIL

POWER DISTRIBUTION NETWORK USING BURIED POWER SUPPLY RAIL

by GEROUSIS VASSILIOS CONSTANTINOS, SENGUPTA RWIK, TRAYNOR KEVIN MICHAEL, HONG JOON GOO
Year of Publication 02.12.2020

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Patent

4T4R 3 4T4R TERNARY WEIGHT CELL WITH HIGH ON/OFF RATIO BACKGROUND

4T4R 3 4T4R TERNARY WEIGHT CELL WITH HIGH ON/OFF RATIO BACKGROUND

by HATCHER RYAN M, KITTL JORGE, SENGUPTA RWIK, RAKSHIT TITASH, HONG JOON GOO, PALLE DHARMENDAR
Year of Publication 10.09.2020

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Patent

3T3R VARIATION RESISTANT 3T3R BINARY WEIGHT CELL WITH LOW OUTPUT CURRENT AND HIGH ON/OFF RATIO

3T3R VARIATION RESISTANT 3T3R BINARY WEIGHT CELL WITH LOW OUTPUT CURRENT AND HIGH ON/OFF RATIO

by HATCHER RYAN M, KITTL JORGE, SENGUPTA RWIK, RAKSHIT TITASH, HONG JOON GOO, PALLE DHARMENDAR
Year of Publication 10.09.2020

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Patent

2T2R 2T2R BINARY WEIGHT CELL WITH HIGH ON/OFF RATIO BACKGROUND

2T2R 2T2R BINARY WEIGHT CELL WITH HIGH ON/OFF RATIO BACKGROUND

by HATCHER RYAN M, KITTL JORGE, SENGUPTA RWIK, RAKSHIT TITASH, HONG JOON GOO, PALLE DHARMENDAR
Year of Publication 28.08.2020

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Patent

METHOD AND SYSTEM FOR PROVIDING A REVERSE-ENGINEERING RESISTANT HARDWARE EMBEDDED SECURITY MODULE

METHOD AND SYSTEM FOR PROVIDING A REVERSE-ENGINEERING RESISTANT HARDWARE EMBEDDED SECURITY MODULE

by SENGUPTA RWIK, HONG JOON GOO, RODDER MARK S, HEDGE GANESH, SIMKA HARSONO S
Year of Publication 11.02.2020

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Patent

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