VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects
Sarangi, S.R., Greskamp, B., Teodorescu, R., Nakano, J., Tiwari, A., Torrellas, J.
Published in IEEE transactions on semiconductor manufacturing (01.02.2008)
Published in IEEE transactions on semiconductor manufacturing (01.02.2008)
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Journal Article
Conference Proceeding
CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging
Sarangi, S.R., Greskamp, B., Torrellas, J.
Published in International Conference on Dependable Systems and Networks (DSN'06) (2006)
Published in International Conference on Dependable Systems and Networks (DSN'06) (2006)
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Conference Proceeding
Energy-Efficient Thread-Level Speculation
Renau, J., Strauss, K., Ceze, L., Liu, W., Sarangi, S.R., Tuck, J., Torrellas, J.
Published in IEEE MICRO (01.01.2006)
Published in IEEE MICRO (01.01.2006)
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Journal Article
Theoretical Framework for Eliminating Redundancy in Workflows
Saha, D., Samanta, A., Sarangi, S.R.
Published in 2009 IEEE International Conference on Services Computing (01.09.2009)
Published in 2009 IEEE International Conference on Services Computing (01.09.2009)
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Conference Proceeding
A Model for Timing Errors in Processors with Parameter Variation
Sarangi, S.R., Greskamp, B., Torrellas, J.
Published in 8th International Symposium on Quality Electronic Design (ISQED'07) (01.03.2007)
Published in 8th International Symposium on Quality Electronic Design (ISQED'07) (01.03.2007)
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Conference Proceeding