A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction
OH, Tae-Young, SOHN, Young-Soo, KIM, Jin-Hyun, KIM, Jin-Kook, KIM, Young-Sik, KIM, Byeong-Cheol, KWAK, Sang-Hyup, LEE, Jae-Hyung, LEE, Jae-Young, SHIN, Chang-Ho, YANG, Yunseok, CHO, Beom-Sig, BAE, Seung-Jun, BANG, Sam-Young, YANG, Hyang-Ja, CHOI, Young-Ryeol, MOON, Gil-Shin, PARK, Cheol-Goo, HWANG, Seok-Won, LIM, Jeong-Don, PARK, Kwang-Ii, JOO SUN CHOI, JUN, Young-Hyun, PARK, Min-Sang, LIM, Ji-Hoon, CHO, Yong-Ki, KIM, Dae-Hyun, KIM, Dong-Min, KIM, Hye-Ran, KIM, Hyun-Joong
Published in IEEE journal of solid-state circuits (01.01.2011)
Published in IEEE journal of solid-state circuits (01.01.2011)
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Conference Proceeding
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW
Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, Si-Hong Kim, Yun-Seok Yang, Dae-Hyun Kim, Sang-Hyup Kwak, Ho-Seok Seol, Chang-Ho Shin, Min-Sang Park, Gong-Heom Han, Byeong-Cheol Kim, Yong-Ki Cho, Hye-Ran Kim, Su-Yeon Doo, Young-Sik Kim, Dong-Seok Kang, Young-Ryeol Choi, Sam-Young Bang, Sun-Young Park, Yong-Jae Shin, Gil-Shin Moon, Cheol-Goo Park, Woo-Seop Kim, Hyang-Ja Yang, Jeong-Don Lim, Kwang-Il Park, Joo Sun Choi, Young-Hyun Jun
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)
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Conference Proceeding
A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction
Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-Hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seok-Won Hwang, Jeong-Don Lim, Kwang-Il Park, Joo Sun Choi, Young-Hyun Jun
Published in 2010 IEEE International Solid-State Circuits Conference - (ISSCC) (01.02.2010)
Published in 2010 IEEE International Solid-State Circuits Conference - (ISSCC) (01.02.2010)
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Conference Proceeding
A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface
Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, Sang-Hyup Kwak, Dong-Min Kim, Dae-Hyun Kim, Young-Sik Kim, Yoo-Seok Yang, Su-Yeon Doo, Jin-Il Lee, Sam-Young Bang, Sun-Young Park, Ki-Woong Yeom, Jae-Young Lee, Hwanwook Park, Woo-Seop Kim, Hyang-Ja Yang, Kwang-Il Park, Joo Sun Choi, Young-Hyun Jun
Published in 2010 Symposium on VLSI Circuits (01.06.2010)
Published in 2010 Symposium on VLSI Circuits (01.06.2010)
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Conference Proceeding