Image segmentation and contour detection using fractal coding
Ida, T., Sambonsugi, Y.
Published in IEEE transactions on circuits and systems for video technology (01.12.1998)
Published in IEEE transactions on circuits and systems for video technology (01.12.1998)
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Journal Article
Image segmentation using fractal coding
Ida, T., Sambonsugi, Y.
Published in IEEE transactions on circuits and systems for video technology (01.12.1995)
Published in IEEE transactions on circuits and systems for video technology (01.12.1995)
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Journal Article
A 320ps access, 3GHz cycle, 144Kb SRAM macro in 90nm CMOS technology using an all-stage reset control signal generator
Akiyoshi, H., Shimizu, H., Matsumoto, T., Kobayashi, K., Sambonsugi, Y.
Published in 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC (2003)
Published in 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC (2003)
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Conference Proceeding
A 100 nm CMOS technology with "sidewall-notched" 40 nm transistors and SiC-capped Cu/VLK interconnects for high performance microprocessor applications
Nakai, S., Takao, Y., Otsuka, S., Sugiyama, K., Ohta, H., Yamanoue, A., Iriyama, Y., Nanjyo, R., Sekino, S., Nagai, H., Naitoh, K., Nakamura, R., Sambonsugi, Y., Tagawa, Y., Horiguchi, N., Yamamoto, T., Kojima, M., Satoh, S., Sugatani, S., Sugii, T., Kase, M., Suzuki, K., Nakaishi, M., Miyajima, M., Ohba, T., Hanyu, I., Yanai, K.
Published in 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) (2002)
Published in 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) (2002)
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Conference Proceeding
0.65 V device design with high-performance and high-density 100 nm CMOS technology for low operation power application
Takao, Y., Nakai, S., Tagawa, Y., Otsuka, S., Sambonsugi, Y., Sugiyama, K., Oota, H., Iriyama, Y., Nanjyo, R., Nagai, H., Naitoh, K., Nakamura, R., Sekino, S., Yamanoue, A., Horiguchi, N., Yamamoto, T., Kojima, M., Satoh, S., Sugii, T., Kase, M., Suzuki, K., Nakaishi, M., Miyajima, M., Ohba, T., Hanyu, I., Sugatani, S.
Published in 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) (2002)
Published in 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) (2002)
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Conference Proceeding
Continuous Scaling Methodology of Planar CMOS Transistors by Suppressing Fluctuation in Carrier Profile
Fukutome, H., Yoshida, E., Tajima, M., Tanaka, T., Sambonsugi, Y., Momiyama, Y.
Published in 2007 IEEE Symposium on VLSI Technology (01.06.2007)
Published in 2007 IEEE Symposium on VLSI Technology (01.06.2007)
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Conference Proceeding
Sub-100-nm Device Fabrication using Proximity X-Ray Lithography at Five Levels
Iba, Yoshihisa, Taguchi, Takao, Kumasaka, Fumiaki, Iizuka, Takashi, Sambonsugi, Yasuhiro, Aoyama, Hajime, Deguchi, Kimiyoshi, Fukuda, Makoto, Oda, Masatoshi, Morita, Hirofumi, Matsuda, Tadahito, Horiuchi, Kei, Matsui, Yasuji
Published in Japanese Journal of Applied Physics (01.12.2000)
Published in Japanese Journal of Applied Physics (01.12.2000)
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Journal Article
Self-affine mapping system for object contour extraction
Ida, T., Sambonsugi, Y.
Published in Proceedings 1999 International Conference on Image Processing (Cat. 99CH36348) (1999)
Published in Proceedings 1999 International Conference on Image Processing (Cat. 99CH36348) (1999)
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Conference Proceeding
A study on millisecond annealing (MSA) induced layout dependence for flash lamp annealing (FLA) and laser spike annealing (LSA) in multiple MSA scheme with 45 nm high-performance technology
Miyashita, T., Kubo, T., Kim, Y.S., Nishikawa, M., Tamura, Y., Mitani, J., Okuno, M., Tanaka, T., Suzuki, H., Sakata, T., Kodama, T., Itakura, T., Idani, N., Mori, T., Sambonsugi, Y., Shimizu, A., Kurata, H., Futatsugi, T.
Published in 2009 IEEE International Electron Devices Meeting (IEDM) (01.12.2009)
Published in 2009 IEEE International Electron Devices Meeting (IEDM) (01.12.2009)
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Conference Proceeding
High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology
Miyashita, T., Ikeda, K., Kim, Y.S., Yamamoto, T., Sambonsugi, Y., Ochimizu, H., Sakoda, T., Okuno, M., Minakata, H., Ohta, H., Hayami, Y., Ookoshi, K., Shimamune, Y., Fukuda, M., Hatada, A., Okabe, K., Tajima, M., Motoh, E., Owada, T., Nakamura, M., Kudo, H., Sawada, T., Nagayama, J., Satoh, A., Mori, T., Hasegawa, A., Kurata, H., Sukegawa, K., Tsukune, A., Yamaguchi, S., Kase, M., Futatsugi, T., Satoh, S., Sugii, T.
Published in 2007 IEEE International Electron Devices Meeting (01.12.2007)
Published in 2007 IEEE International Electron Devices Meeting (01.12.2007)
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Conference Proceeding
Realization of 0.1 /spl mu/m buried-channel PMOSFETs by device restructuring using tilted well implantation technology
Tanaka, T., Momiyama, Y., Goto, K., Sambonsugi, Y., Deura, M., Sugii, T.
Published in 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) (1999)
Published in 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) (1999)
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Conference Proceeding
A perfect process compatible 2.49 /spl mu/m/sup 2/ embedded SRAM cell technology for 0.13 /spl mu/m-generation CMOS logic LSIs
Sambonsugi, Y., Maruyama, T., Yano, K., Sakaue, H., Yamamoto, H., Kawamura, E., Ohkubo, S., Tamura, Y., Sugii, T.
Published in 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) (1998)
Published in 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) (1998)
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Conference Proceeding
A 4-um/su 2/ Full-CMOS SRAM Cell Technology For 0.2-um High-performance Logic LSIs
Takao, Y., Sambonsugi, Y., Watanabe, K., Takatsuka, H., Karasawa, T., Kawamura, E., Hashimoto, K., Takagi, H., Inoue, F., Shimizu, H., Yamazaki, T., Goto, H., Sugii, T., Miyajima, M., Watanabe, K., Aoyama, K.
Published in 1997 Symposium on VLSI Technology (1997)
Published in 1997 Symposium on VLSI Technology (1997)
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Conference Proceeding