Method to improve latchup by forming selective sloped staircase STI structure to use in the I/0 or latchup sensitive area
KEUNG LEUNG YING, ZHENG JIA ZHEN, SUNDARESAN RAVI, YANG PAN, MENG JAMES LEE YONG, PRADEEP YELEHANKA RAMACHANDRAMURTHY, QUEK ELGIN, CHAN LAP
Year of Publication 23.01.2003
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Year of Publication 23.01.2003
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METHOD FOR FORMING TRANSISTOR HAVING RAISED SOURCE/DRAIN AREA
KEUNG LEUNG YING, RAP CHAN, SUNDARESAN RAVI, ZHENG JIA ZHEN, PAN YANG, MENG JAMES LEE YONG, PRADEEP YELEHANKA RAMACHANDRAMURTHY, QUEK ELGIN
Year of Publication 10.01.2003
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Year of Publication 10.01.2003
Patent
Method for forming variable-K gate dielectric
ZHENG JIA ZHEN, SUNDARESAN RAVI, LEUNG YING KEUNG, PAN YANG, LEE JAMES YONG MENG, PRADEEP YELEHANKA RAMACHANDRAMURTHY, QUEK ELGIN, CHAN LAP
Year of Publication 21.11.2002
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Year of Publication 21.11.2002
Patent
A method to form a low parasitic capacitance CMOS device
SUNDARESAN, RAVI, RAMACHANDRAMURTHY PRADEEP, YELEHANKA, QUEK, ELGIN, CHAN, LAP, KEUNG LEUNG, YING, ZHEN ZHENG, JIA, YONG MENG LEE, JAMES, PAN, YANG
Year of Publication 06.11.2002
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Year of Publication 06.11.2002
Patent
METHOD FOR MANUFACTURING MOS TRANSISTOR
RAP CHAN, SUNDARESAN RAVI, ZHENG JIA ZHEN, LEUNG YING KEUNG, PAN YANG, LEE JAMES YONG MENG, PRADEEP YELEHANKA RAMACHANDRAMURTHY, QUEK ELGIN
Year of Publication 25.10.2002
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Year of Publication 25.10.2002
Patent
Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth
Pradeep, Yelehanka Ramachandramurthy, Zheng, Jia Zhen, Chan, Lap, Quek, Elgin, Sundaresan, Ravi, Pan, Yang, Lee, James Yong Meng, Leung, Ying Keung
Year of Publication 08.10.2002
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Year of Publication 08.10.2002
Patent
METHOD FOR FORMING TRANSISTOR GATE DIELECTRIC HAVING HIGH DIELECTRIC CONSTANT REGION AND LOW DIELECTRIC CONSTANT REGION
RAP CHAN, ZHENG JIA ZHEN, SUNDARESAN RAVI, LEUNG YING KEUNG, PAN YANG, LEE JAMES YONG MENG, PRADEEP YELEHANKA RAMACHANDRAMURTHY, QUEK ELGIN
Year of Publication 04.10.2002
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Year of Publication 04.10.2002
Patent
MANUFACTURING METHOD FOR GATE ELECTRODE
RAP CHAN, SUNDARESAN RAVI, ZHENG JIA ZHEN, LEUNG YING KEUNG, PAN YANG, LEE JAMES YONG MENG, PRADEEP YELEHANKA RAMACHANDRAMURTHY, QUEK ELGIN
Year of Publication 04.10.2002
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Year of Publication 04.10.2002
Patent
Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)
Zheng, Jia Zhen, Chan, Lap, Quek, Elgin, Sundaresan, Ravi, Pan, Yang, Lee, James Yong Meng, Leung, Ying Keung, Pradeep, Yelehanka Ramachandramurthy
Year of Publication 24.09.2002
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Year of Publication 24.09.2002
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Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)
ZHENG JIA ZHEN, SUNDARESAN RAVI, LEUNG YING KEUNG, PAN YANG, LEE JAMES YONG MENG, PRADEEP YELEHANKA RAMACHANDRAMURTHY, QUEK ELGIN, CHAN LAP
Year of Publication 24.09.2002
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Year of Publication 24.09.2002
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METHOD FOR FORMING BUBBLE-LIKE SHALLOW TRENCH SEPARATION, USING MICROMACHINING TECHNOLOGY TO REMOVE HEAVILY-DOPED SILICON
RAP CHAN, ZHENG JIA ZHEN, SUNDARESAN RAVI, LEUNG YING KEUNG, PAN YANG, LEE JAMES YONG MENG, PRADEEP YELEHANKA RAMACHANDRAMURTHY, QUEK ELGIN
Year of Publication 20.09.2002
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Year of Publication 20.09.2002
Patent
METHOD OF MANUFACTURING GATE DIELECTIC AND SEMICONDUCTOR GATE
RAP CHAN, ZHENG JIA ZHEN, SUNDARESAN RAVI, LEUNG YING KEUNG, PAN YANG, LEE JAMES YONG MENG, PRADEEP YELEHANKA RAMACHANDRAMURTHY, QUEK ELGIN
Year of Publication 20.09.2002
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Year of Publication 20.09.2002
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