A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS
Chun-Yuan Cheng, Jinn-Shyan Wang, Pei-Yuan Chou, Shiou-Ching Chen, Chi-Tien Sun, Yuan-Hua Chu, Tzu-Yi Yang
Published in 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) (01.11.2014)
Published in 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) (01.11.2014)
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