Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches
BORER TERRY, BROWN STEPHEN D, LEAVER ANDREW, KARCHMER DAVID, QUAN GABRIEL
Year of Publication 21.08.2012
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Year of Publication 21.08.2012
Patent
Method and apparatus for performing post-placement routability optimization
BROWN STEPHEN D, SINGH DESHANAND, CHIU GORDON RAYMOND, MANOHARARAJAH VALAVAN
Year of Publication 17.11.2009
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Year of Publication 17.11.2009
Patent
Method and apparatus for performing post-placement routability optimization
Manohararajah, Valavan, Chiu, Gordon Raymond, Singh, Deshanand, Brown, Stephen D
Year of Publication 17.11.2009
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Year of Publication 17.11.2009
Patent
Incremental placement for structured ASICs using the transportation problem
Ling, Andrew C., Singh, Deshanand P, Brown, Stephen D.
Published in 2007 IFIP International Conference on Very Large Scale Integration (01.10.2007)
Published in 2007 IFIP International Conference on Very Large Scale Integration (01.10.2007)
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Conference Proceeding
Method and apparatus for performing multiple stage physical synthesis
Singh, Deshanand, Manohararajah, Valavan, Chiu, Gordon Raymond, Blunno, Ivan, Brown, Stephen D
Year of Publication 09.08.2011
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Year of Publication 09.08.2011
Patent
Method and apparatus for performing multiple stage physical synthesis
BLUNNO IVAN, BROWN STEPHEN D, SINGH DESHANAND, CHIU GORDON RAYMOND, MANOHARARAJAH VALAVAN
Year of Publication 09.08.2011
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Year of Publication 09.08.2011
Patent
BddCut: Towards Scalable Symbolic Cut Enumeration
Ling, A.C., Jianwen Zhu, Brown, S.D.
Published in 2007 Asia and South Pacific Design Automation Conference (01.01.2007)
Published in 2007 Asia and South Pacific Design Automation Conference (01.01.2007)
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Conference Proceeding
Modular Partitioning for Incremental Compilation
Mehrdad Eslami Dehkordi, Brown, S.D., Borer, T.
Published in 2006 International Conference on Field Programmable Logic and Applications (01.08.2006)
Published in 2006 International Conference on Field Programmable Logic and Applications (01.08.2006)
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Conference Proceeding
Adaptive FPGAs: High-Level Architecture and a Synthesis Method
Valavan Manohararajah, Brown, S.D., Vranesic, Z.G.
Published in 2006 International Conference on Field Programmable Logic and Applications (01.08.2006)
Published in 2006 International Conference on Field Programmable Logic and Applications (01.08.2006)
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Conference Proceeding
Mouse chromosome 7
Rinchik, E M, Magnuson, T, Holdener-Kenny, B, Kelsey, G, Bianchi, A, Conti, C J, Chartier, F, Brown, K A, Brown, S D, Peters, J
Published in Mammalian genome (1992)
Published in Mammalian genome (1992)
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Journal Article
Experiences with soft-core processor design
Plavec, F., Fort, B., Vranesic, Z.G., Brown, S.D.
Published in 19th IEEE International Parallel and Distributed Processing Symposium (2005)
Published in 19th IEEE International Parallel and Distributed Processing Symposium (2005)
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Conference Proceeding
Mapping Arbitrary Logic Functions into Synchronous Embedded Memories For Area Reduction on FPGAs
Chiu, G.R., Singh, D.P., Manohararajah, V., Brown, S.D.
Published in 2006 IEEE/ACM International Conference on Computer Aided Design (01.11.2006)
Published in 2006 IEEE/ACM International Conference on Computer Aided Design (01.11.2006)
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Conference Proceeding
Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches
BORER TERRY, BROWN STEPHEN D, LEAVER ANDREW, KARCHMER DAVID, QUAN GABRIEL
Year of Publication 23.02.2010
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Year of Publication 23.02.2010
Patent