Search Results - "SRIDHAR. CHERUKU" :: K.UTB vyhledávací portál

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LEVEL SHIFTER AND ELECTRONIC DEVICE

by CHERUKU, Sridhar, SHAIK, Hussainvali, SUBRAMANIAN, Sivaramakrishnan
Year of Publication 21.09.2023

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Physical interface and associated signal processing method for clock domain transfer of quarter-rate data

by Cheruku, Sridhar, Subramanian, Sivaramakrishnan, Shaik, Hussainvali, Chao, Ko-Ching
Year of Publication 19.03.2024

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PHYSICAL INTERFACE AND ASSOCIATED SIGNAL PROCESSING METHOD FOR CLOCK DOMAIN TRANSFER OF QUARTER-RATE DATA

by Cheruku, Sridhar, Subramanian, Sivaramakrishnan, Shaik, Hussainvali, Chao, Ko-Ching
Year of Publication 10.08.2023

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Gate signal control circuit for DDR memory system

by Cheruku, Sridhar, Wu, Hong-Yi, Subramanian, Sivaramakrishnan, Chao, Ko-Ching
Year of Publication 14.06.2022

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Method for controlling multi-cycle write leveling process in memory system

by Cheruku, Sridhar, Wu, Hong-Yi, Subramanian, Sivaramakrishnan, Chao, Ko-Ching
Year of Publication 12.10.2021

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Duty-cycle correction circuit for DDR devices

by Cheruku, Sridhar, Mohanta, Sandeep Kumar, Subramanian, Sivaramakrishnan, Shaik, Hussainvali
Year of Publication 11.05.2021

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Level shifter and electronic device

by SUBRAMANIAN, SIVARAMAKRISHNAN, CHERUKU, SRIDHAR, SHAIK, HUSSAINVALI
Year of Publication 01.10.2023

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Level shifter and electronic device

by SUBRAMANIAN, SIVARAMAKRISHNAN, CHERUKU, SRIDHAR, SHAIK, HUSSAINVALI
Year of Publication 01.10.2023

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GATE SIGNAL CONTROL CIRCUIT FOR DDR MEMORY SYSTEM

by CHERUKU, Sridhar, WU, Hong-Yi, CHAO, Ko-Ching, SUBRAMANIAN, Sivaramakrishnan
Year of Publication 26.05.2022

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Physical layer and data processing method

by SUBRAMANIAN, SIVARAMAKRISHNAN, CHERUKU, SRIDHAR, CHAO, KOING, SHAIK, HUSSAINVALI
Year of Publication 16.08.2023

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Physical layer and data processing method

by SHAIKH HOSSEIN WALIL, SUBRAMANIAN SIVARAMAKRISHNAN, SRIDHAR. CHERUKU, ZHAO KEQING
Year of Publication 11.08.2023

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Physical layer and data processing method

by SUBRAMANIAN, SIVARAMAKRISHNAN, CHERUKU, SRIDHAR, CHAO, KOING, SHAIK, HUSSAINVALI
Year of Publication 01.07.2023

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Duty-cycle correction circuit for DDR devices

by SUBRAMANIAN, SIVARAMAKRISHNAN, CHERUKU, SRIDHAR, MOHANTA, SANDEEP KUMAR, SHAIK, HUSSAINVALI
Year of Publication 16.03.2022

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Duty-cycle correction circuit for ddr devices

by SUBRAMANIAN, SIVARAMAKRISHNAN, CHERUKU, SRIDHAR, MOHANTA, SANDEEP KUMAR, SHAIK, HUSSAINVALI
Year of Publication 11.10.2021

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Signal phase delay chain with calibration, bypass and digital comparator circuits

by SIVARAMAKRISHNAN SUBRAMANIAN, NIDHIR KUMAR, SRIDHAR CHERUKU
Year of Publication 09.07.2014

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Calibration of delay chains

by KUMAR NIDHIR, CHERUKU SRIDHAR, SUBRAMANIAN SIVARAMAKRISHNAN
Year of Publication 08.07.2014

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CALIBRATION OF DELAY CHAINS

by KUMAR NIDHIR, CHERUKU SRIDHAR, SUBRAMANIAN SIVARAMAKRISHNAN
Year of Publication 22.05.2014

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Receiver circuit with high input voltage protection

by KUMAR NIDHIR, CHERUKU SRIDHAR, DWIVEDI SANDEEP
Year of Publication 06.08.2013

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Reduced quantization error I/O resistor calibrator

by KUMAR NIDHIR, CHERUKU SRIDHAR, SUBRAMANIAN SIVARAMAKRISHNAN
Year of Publication 23.04.2013

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Apparatus and method providing an interface between a first voltage domain and a second voltage domain

by PRABHU MANJUNATHA GOVINDA, KUMAR NIDHIR, CHERUKU SRIDHAR
Year of Publication 16.04.2013

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