Retiming revisited and reversed
Even, G., Spillinger, I.Y., Stok, L.
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.03.1996)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.03.1996)
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Journal Article
Performance evaluation of a decoded instruction cache for variable instruction-length computers
Intrater, Gideon, Spillinger, Ilan
Published in Computer Architecture (19th International Symposium) (01.05.1992)
Published in Computer Architecture (19th International Symposium) (01.05.1992)
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Conference Proceeding
Journal Article
Delay test generation. I. Concepts and coverage metrics
Iyengar, V.S., Rosen, B.K., Spillinger, I.
Published in International Test Conference 1988 Proceeding@m_New Frontiers in Testing (1988)
Published in International Test Conference 1988 Proceeding@m_New Frontiers in Testing (1988)
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Conference Proceeding
Architectural Improvements for a Data-Driven VLSI Processing Array
Weiss, S., Spillinger, I.Y., Silberman, G.M.
Published in Journal of parallel and distributed computing (01.12.1993)
Published in Journal of parallel and distributed computing (01.12.1993)
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Journal Article
Delay test generation. II. Algebra and algorithms
Iyengar, V.S., Rosen, B.K., Spillinger, I.
Published in International Test Conference 1988 Proceeding@m_New Frontiers in Testing (1988)
Published in International Test Conference 1988 Proceeding@m_New Frontiers in Testing (1988)
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Conference Proceeding
Logic synthesis for logic array modules
SPILLINGER; ILAN YITSHAK, DAMIANO; ROBERT, TREVILLYAN; LOUISE HELEN, VAN GINNEKEN; LUKAS PAUL PIETER PEPIJN
Year of Publication 19.05.1998
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Year of Publication 19.05.1998
Patent