A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme
Yong-Cheol Bae, Joon-Young Park, Sang Jae Rhee, Seung Bum Ko, Yonggwon Jeong, Kwang-Sook Noh, Younghoon Son, Jaeyoun Youn, Yonggyu Chu, Hyunyoon Cho, Mijo Kim, Daesik Yim, Hyo-Chang Kim, Sang-Hoon Jung, Hye-In Choi, Sungmin Yim, Jung-Bae Lee, Joo Sun Choi, Kyungseok Oh
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
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Conference Proceeding
Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM
Chang-Kyo Lee, Junha Lee, Ki-Ho Kim, Jin-Seok Heo, Gil-Hoon Cha, Jin-Hyeok Baek, Dae-Sik Moon, Yoon-Joo Eom, Tae-Sung Kim, Hyunyoon Cho, Younghoon Son, Seonghwan Kim, Jong-Wook Park, Sewon Eom, Si-Hyeong Cho, Young-Ryeol Choi, Seungseob Lee, Kyoung-Soo Ha, Youngseok Kim, Bo-Tak Lim, Dae-Hee Jung, Eungsung Seo, Kyoung-Ho Kim, Yoon-Gyu Song, Youn-Sik Park, Tae-Young Oh, Seung-Jun Bae, In-Dal Song, Seok-Hun Hyun, Joon-Young Park, Hyuck-Joon Kwon, Young-Soo Sohn, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang
Published in 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) (01.11.2017)
Published in 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) (01.11.2017)
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Conference Proceeding
A 3.0 Gb/s/pin 4th generation F-chip with Toggle 5.0 Specification for 16Tb NAND Flash Memory Multi chip Package
Jo, Youngmin, Kavala, Anil, Kim, Tongsung, Chun, Byungkwan, Park, Jung-June, Lee, Taesung, Seo, Jungmin, Yang, Manjae, Park, Taehyeon, Kwon, Hyunjin, Lee, Cheolhui, Son, Younghoon, Kwak, Junghwan, Lee, Younggyu, Ku, Hwan Seok, Na, Daehoon, Yu, Changyeon, Park, Jonghoon, Kim, JaeHwan, Kwon, Hyojin, Kim, Chanho, Jung, Moon-Ki, Park, Chanjin, Seo, Donghyun, Kim, Moosung, Lee, Seungjae, Lee, Jin-Yub, Kang, Dongku, Yoon, Chiweon, Hur, SungHoi
Published in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (11.06.2023)
Published in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (11.06.2023)
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Conference Proceeding
23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power
Ha, Kyung-Soo, Lee, Chang-Kyo, Lee, Dongkeon, Moon, Daesik, Jang, Jin-Hun, Hwang, Hyong-Ryol, Chi, Hyungjoon, Park, Junghwan, Shin, Seungjun, Park, Dukha, Kim, Sang-Yun, Lim, Sukhyun, Park, Kiwon, Choi, YeonKyu, Kim, Young-Hwa, Son, Younghoon, Cho, Hyunyoon, Na, Byongwook, Ahn, Hyo-Joo, Lee, Seungseob, Choi, Seouk-Kyu, Park, Youn-Sik, Hyun, Seok-Hun, Chang, Soobong, Kwon, Hyuck-Joon, Choi, Jung-Hwan, Oh, Tae-Young, Sohn, Young-Soo, Park, Kwang-II, Jang, Seong-Jin
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
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Conference Proceeding
22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process
Chi, Hyung-Joon, Lee, Chang-Kyo, Park, Junghwan, Heo, Jin-Seok, Jung, Jaehoon, Lee, Dongkeon, Kim, Dae-Hyun, Park, Dukha, Kim, Kihan, Kim, Sang-Yun, Park, Jinsol, Cho, Hyunyoon, Lim, Sukhyun, Choi, YeonKyu, Lim, Youngil, Moon, Daesik, Park, Geuntae, Jang, Jin-Hun, Lee, Kyungho, Hwang, Isak, Kim, Cheol, Son, Younghoon, Kang, Gil-Young, Park, Kiwon, Lee, Seungjun, Doo, Su-Yeon, Shin, Chang-Ho, Na, Byongwook, Kwon, Jisuk, Kim, Kyung Ryun, Choi, Hyein, Choi, Seouk-Kyu, Chang, Soobong, Bae, Wonil, Kwon, Hyuck-Joon, Sohn, Young-Soo, Bae, Seung-Jun, Park, Kwang-Il, Lee, Jung-Bae
Published in 2020 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2020)
Published in 2020 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2020)
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Conference Proceeding
Display device
Kim, Daehee, Park, JiYoung, Son, YoungHoon, Heo, JoonYoung, Choi, Hyeju
Year of Publication 28.05.2024
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Year of Publication 28.05.2024
Patent
MEMORY DEVICES CONFIGURED TO GENERATE PULSE AMPLITUDE MODULATION-BASED DQ SIGNALS, MEMORY CONTROLLERS, AND MEMORY SYSTEMS INCLUDING THE MEMORY DEVICES AND THE MEMORY CONTROLLERS
SON, Younghoon, LEE, Sucheol, CHOI, Junghwan, CHO, Hyunyoon, CHOI, Youngdon
Year of Publication 13.03.2024
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Year of Publication 13.03.2024
Patent
Apparatus, memory device, and method reducing clock training time
Yu, Seongheon, Kim, Sangwoo, Kim, Chulung, Son, Younghoon, Kim, Joungyeal
Year of Publication 05.03.2024
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Year of Publication 05.03.2024
Patent
Translation device, test system including the same, and memory system including the translation device
Cho, Hyunyoon, Choi, Youngdon, Choi, Junghwan, Jin, Hyungmin, Son, Younghoon
Year of Publication 09.01.2024
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Year of Publication 09.01.2024
Patent
MEMORY DEVICE, METHOD OF CALIBRATING SIGNAL LEVEL THEREOF, AND MEMORY SYSTEM HAVING THE SAME
Park, Jaewoo, Um, Youngdo, Choi, Youngdon, Choi, Junghwan, Son, Younghoon
Year of Publication 28.12.2023
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Year of Publication 28.12.2023
Patent