Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle
Vincent, Benjamin, Hathwar, Raghu, Kamon, Mattan, Ervin, Joseph, Schram, Tom, Chiarella, Thomas, Demuynck, Steven, Baudot, Sylvain, Siew, Yong Kong, Kubicek, Stenfan, Litta, Eugenio Dentoni, Chew, SoonAik, Mitard, Jerome
Published in IEEE transactions on electron devices (01.12.2020)
Published in IEEE transactions on electron devices (01.12.2020)
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Journal Article
Predictive and prospective calibrated TCAD to improve device performances in sub-20 nm gate length p-FinFETs
Eyben, Pierre, De Keersgieter, An, Matagne, Philippe, Chiarella, Thomas, Porret, Clément, Hikavyy, Andriy, Siew, Yong Kong, Goux, Ludovic, Mitard, Jérôme, Horiguchi, Naoto
Published in Japanese Journal of Applied Physics (01.04.2024)
Published in Japanese Journal of Applied Physics (01.04.2024)
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Journal Article
Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling
Gupta, Anshul, Pedreira, Olalla Varela, Arutchelvan, Goutham, Zahedmanesh, Houman, Devriendt, Katia, Mertens, Hans, Tao, Zheng, Ritzenthaler, Romain, Wang, Shouhua, Radisic, Dunja, Kenis, Karine, Teugels, Lieve, Sebai, Farid, Lorant, Christophe, Jourdan, Nicolas, Chan, Boon Teik, Subramanian, Sujith, Schleicher, Filip, Hopf, Toby, Peter, Antony Premkumar, Rassoul, Nouredine, Debruyn, Haroen, Demonie, Ingrid, Siew, Yong Kong, Chiarella, Thomas, Briggs, Basoene, Zhou, Xiuju, Rosseel, Erik, De Keersgieter, An, Capogreco, Elena, Litta, Eugenio Dentoni, Boccardi, Guillaume, Baudot, Sylvain, Mannaert, Geert, Bontemps, Noemie, Sepulveda, A., Mertens, Sofie, Kim, Min-Soo, Dupuy, Emmanuel, Vandersmissen, Kevin, Paolillo, Sara, Yakimets, Dmitry, Chehab, Bilal, Favia, Paola, Drijbooms, Christel, Cousserier, Joris, Jaysankar, Manoj, Lazzarino, Frederic, Morin, Pierre, Altamirano, Efrain, Mitard, Jerome, Wilson, Christopher J., Holsteyns, Frank, Boemmels, Juergen, Demuynck, Steven, Tokei, Zsolt, Horiguchi, Naoto
Published in IEEE transactions on electron devices (01.12.2020)
Published in IEEE transactions on electron devices (01.12.2020)
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Journal Article
Scalability of RuTiN barriers deposited by plasma-enhanced atomic layer deposition for advanced interconnects
Swerts, Johan, Siew, Yong-Kong, Van Besien, Els, Barbarin, Yohan, Opsomer, Karl, Bömmels, Jürgen, Tőkei, Zsolt, Van Elshocht, Sven
Published in Microelectronic engineering (25.05.2014)
Published in Microelectronic engineering (25.05.2014)
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Conference Proceeding
Plasma Enhanced Chemical Vapor Deposition of Manganese on Low-k Dielectrics for Copper Diffusion Barrier Application
Jourdan, Nicolas, Barbarin, Yohan, Croes, Kristof, Kong Siew, Yong, Van Elshocht, Sven, Tőkei, Zsolt, Vancoille, Eric
Published in ECS solid state letters (01.01.2013)
Published in ECS solid state letters (01.01.2013)
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Journal Article
Impact of advanced patterning options, 193nm and EUV, on local interconnect performance
Stucchi, M., Tokei, Z., Demuynck, S., Yong-Kong Siew
Published in 2012 IEEE International Interconnect Technology Conference (01.06.2012)
Published in 2012 IEEE International Interconnect Technology Conference (01.06.2012)
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Conference Proceeding
Alternative metals for advanced interconnects
Adelmann, Christoph, Liang Gong Wen, Peter, Antony Premkumar, Yong Kong Siew, Croes, Kristof, Swerts, Johan, Popovici, Mihaela, Sankaran, Kiroubanand, Pourtois, Geoffrey, Van Elshocht, Sven, Bommels, Jurgen, Tokei, Zsolt
Published in IEEE International Interconnect Technology Conference (01.05.2014)
Published in IEEE International Interconnect Technology Conference (01.05.2014)
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Conference Proceeding
Full reliability study of advanced metallization options for 30nm ½pitch interconnects
Croes, Kristof, Demuynck, Steven, Siew, Yong Kong, Pantouvaki, Marianna, Wilson, Christopher J., Heylen, Nancy, Beyer, Gerald P., Tőkei, Zsolt
Published in Microelectronic engineering (01.06.2013)
Published in Microelectronic engineering (01.06.2013)
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Journal Article
Integration of 20nm half pitch single damascene copper trenches by spacer-defined double patterning (SDDP) on metal hard mask (MHM)
Yong Kong Siew, Versluijs, Janko, Kunnen, Eddy, Ciofi, Ivan, Alaerts, Wilfried, Dekkers, Harold, Volders, Henny, Suhard, Samuel, Cockburn, Andrew, Sleeckx, Erik, Van Besien, Els, Struyf, Herbert, Maenhoudt, Mireille, Noori, Atif, Padhi, Deenesh, Shah, Kavita, Gravey, Virginie, Beyer, Gerald
Published in 2010 IEEE International Interconnect Technology Conference (01.06.2010)
Published in 2010 IEEE International Interconnect Technology Conference (01.06.2010)
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Conference Proceeding
Method for fabricating an air gap shallow trench isolation structure
ANG TINGONG, LIM VICTOR SENGKEONG, SEE ALEX, TEH YOUNG-WAY, SIEW YONG KONG
Year of Publication 01.06.2002
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Year of Publication 01.06.2002
Patent
Line Edge Roughness (LER) correlation and dielectric reliability with Spacer-Defined Double Patterning (SDDP) at 20nm half pitch
Yong Kong Siew, Stucchi, M., Versluijs, J., Roussel, P., Kunnen, E., Pantouvaki, M., Beyer, G. P., Tokei, Z.
Published in 2011 IEEE International Interconnect Technology Conference (01.05.2011)
Published in 2011 IEEE International Interconnect Technology Conference (01.05.2011)
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Conference Proceeding