A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs
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Published in 2012 Symposium on VLSI Circuits (VLSIC) (01.06.2012)
Published in 2012 Symposium on VLSI Circuits (VLSIC) (01.06.2012)
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Year of Publication 14.08.2014
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Year of Publication 25.01.2012
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Year of Publication 25.01.2012
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Year of Publication 25.01.2012
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