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"SHIELL, JONATHAN H"
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"SHIELL, JONATHAN H"
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Data prefetch apparatus and method
by
CAI, GEORGE Z.N
,
SHIELL
,
JONATHAN H
Year of Publication
17.08.2011
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Instruction set architecture with versatile adder carry control
by
SHIELL JONATHAN H
Year of Publication
18.06.2002
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Instruction set architecture with versatile adder carry control
by
Shiell
,
Jonathan H
Year of Publication
18.06.2002
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Microprocessor system with block move circuit disposed between cache circuits
by
SHIELL JONATHAN H
Year of Publication
03.04.2001
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Emulation devices utilizing state machines
by
SHIELL
;
JONATHAN H
Year of Publication
21.03.2000
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Superscalar microprocessor having combined register and memory renaming circuits, systems, and methods
by
SHIELL
;
JONATHAN H
Year of Publication
08.06.1999
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Microprocessor using combined actual and speculative branch history prediction
by
SHIELL
;
JONATHAN H
Year of Publication
26.01.1999
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Mikroprozessor mit Mitteln zur Speicherung von nicht-cachespeicherbaren Daten
by
SHIELL
,
JONATHAN H
,
KRUEGER, STEVEN D
Year of Publication
25.11.2004
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SMM power management circuits, systems, and methods
by
CHEN; IAN
,
SHIELL
;
JONATHAN H
Year of Publication
16.05.2000
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Mikroprozessor mit einem Nachschreibcachespeicher
by
MARSHALL, JR
,
SHIELL
,
JONATHAN H
Year of Publication
12.02.2004
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Single chip microprocessor circuits, systems, and methods for self-loading patch micro-operation codes and patch microinstruction codes
by
CHEN; IAN
,
SHIELL
;
JONATHAN H
Year of Publication
07.09.1999
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Microprocessor comprising means for storing non-cacheable data
by
SHIELL
,
JONATHAN H
,
KRUEGER, STEVEN D
Year of Publication
02.01.2004
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Method and system for single cycle execution of successive iterations of a loop
by
ANDERSON, TIMOTHY D
,
SHIELL
,
JONATHAN H
Year of Publication
08.01.2003
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Selectively powering X Y organized memory banks
by
Shiell
,
Jonathan H
,
Steiss, Donald E
Year of Publication
27.08.2002
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Selectively powering X Y organized memory banks
by
STEISS DONALD E
,
SHIELL JONATHAN H
Year of Publication
27.08.2002
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Microprocessor circuits, systems, and methods for conditioning information prefetching based on resource burden
by
Bondi, James O
,
Shiell
,
Jonathan H
Year of Publication
04.06.2002
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Microprocessor circuits, systems, and methods for conditioning information prefetching based on resource burden
by
BONDI JAMES O
,
SHIELL JONATHAN H
Year of Publication
04.06.2002
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Data processor having memory access unit with predetermined number of instruction cycles between activation and initial data transfer
by
BOSSHART PATRICK W
,
SHIELL JONATHAN H
Year of Publication
08.01.2002
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Data processor having memory access unit with predetermined number of instruction cycles between activation and initial data transfer
by
Shiell
,
Jonathan H
,
Bosshart, Patrick W
Year of Publication
08.01.2002
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Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism
by
BARTLEY DAVID H
,
SHIELL JONATHAN H
Year of Publication
13.11.2001
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