A High-Speed 4×4 Bit Parallel Multiplier using Selectively Doped Heterostructure Transistors
Schlier, A. R., Pei, S. S., Shah, N. J., Tu, C. W., Mahoney, G. E.
Published in 1985 IEEE GaAs IC Symposium Technical Digest (01.11.1985)
Published in 1985 IEEE GaAs IC Symposium Technical Digest (01.11.1985)
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