Search Results - "SCHEEVEL MARK" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

Method and system for automatic cache management

Method and system for automatic cache management

by SCHEEVEL MARK R, RAJKUMAR N. ISAAC, O'CONNELL CONLETH
Year of Publication 15.04.2008

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Patent

Method and system for automatic cache management

Method and system for automatic cache management

by O'Connell, Conleth, Scheevel, Mark R, Rajkumar, N. Isaac
Year of Publication 15.04.2008

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Patent

System, method and computer program product for automatically updating content in a cache

System, method and computer program product for automatically updating content in a cache

by SCHEEVEL MARK R, AFSHAR, JR. JAMSHID, O'CONNELL, JR. CONLETH S, LARSEN BRETT J, CALDWELL DAVID DEAN, RAJKUMAR NEWTON ISAAC, SHEPSTONE LEE, YOU PUHONG
Year of Publication 28.05.2013

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Patent

METHOD AND SYSTEM FOR CACHE MANAGEMENT

METHOD AND SYSTEM FOR CACHE MANAGEMENT

by SCHEEVEL MARK R, AFSHAR, JR. JAMSHID, O'CONNELL, JR. CONLETH S, LARSEN BRETT J, CALDWELL DAVID DEAN, RAJKUMAR NEWTON ISAAC, SHEPSTONE LEE, YOU PUHONG
Year of Publication 10.02.2011

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Patent

Method and system for cache management

Method and system for cache management

by Shepstone, Lee, O'Connell, Jr, Conleth S, Scheevel, Mark R, Rajkumar, Newton Isaac, Afshar, Jr, Jamshid, You, Puhong, Larsen, Brett J, Caldwell, David Dean
Year of Publication 19.10.2010

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Patent

Method and system for cache management

Method and system for cache management

by SCHEEVEL MARK R, AFSHAR, JR. JAMSHID, O'CONNELL, JR. CONLETH S, LARSEN BRETT J, CALDWELL DAVID DEAN, RAJKUMAR NEWTON ISAAC, SHEPSTONE LEE, YOU PUHONG
Year of Publication 19.10.2010

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Patent

CONDITION CONCENTRATOR AND CONTROL STORE FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES

CONDITION CONCENTRATOR AND CONTROL STORE FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES

by LOGSDON, GARY LEE, SCHEEVEL, MARK ROBERT
Year of Publication 30.08.1989

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Patent

CONDITION CONCENTRATOR AND CONTROL STORE FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES

CONDITION CONCENTRATOR AND CONTROL STORE FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES

by LOGSDON, GARY L, SCHEEVEL, MARK R
Year of Publication 10.11.1987

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Patent

Condition concentrator and control store for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes

Condition concentrator and control store for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes

by SCHEEVEL; MARK R, LOGSDON; GARY L
Year of Publication 30.09.1986

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Patent

Condition concentrator and control store for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes

Condition concentrator and control store for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes

by LOGSDON, GARY LEE, SCHEEVEL, MARK ROBERT
Year of Publication 18.12.1985

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Patent

PARALLEL REGISTER TRANSFER MECHANISM FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES

PARALLEL REGISTER TRANSFER MECHANISM FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES

by BOLTON, BRUCE CECIL, LOGSDON, GARY LEE, SCHEEVEL, MARK ROBERT
Year of Publication 11.08.1993

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Patent

SYSTEM MEMORY FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES

SYSTEM MEMORY FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES

by WINCHELL, MICHAEL A, LOGSDON, GARY L, SCHEEVEL, MARK R
Year of Publication 16.12.1992

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Patent

SYSTEM MEMORY FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES

SYSTEM MEMORY FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES

by WINCHELL, MICHAEL A, LOGSDON, GARY L, SCHEEVEL, MARK R
Year of Publication 02.01.1990

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Patent

PARALLEL REGISTER TRANSFER MECHANISM FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES

PARALLEL REGISTER TRANSFER MECHANISM FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES

by BOLTON, BRUCE CECIL, LOGSDON, GARY LEE, SCHEEVEL, MARK ROBERT
Year of Publication 13.09.1989

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Patent

SYSTEM MEMORY FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES

SYSTEM MEMORY FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES

by WINCHELL, MICHAEL A, LOGSDON, GARY L, SCHEEVEL, MARK R
Year of Publication 30.08.1989

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Patent

PARALLEL REGISTER TRANSFER MECHANISM FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES

PARALLEL REGISTER TRANSFER MECHANISM FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES

by LOGSDON, GARY L, BOLTON, BRENT C, SCHEEVEL, MARK R
Year of Publication 12.04.1988

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Patent

Parallel register transfer mechanism for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes

Parallel register transfer mechanism for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes

by SCHEEVEL; MARK R, BOLTON; BRENT C, LOGSDON; GARY L
Year of Publication 31.03.1987

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Patent

System memory for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes

System memory for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes

by SCHEEVEL; MARK R, WINCHELL; MICHAEL A, LOGSDON; GARY L
Year of Publication 07.10.1986

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Patent

SYSTEM MEMORY FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES

SYSTEM MEMORY FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES

by LOGSDON, GARY, L, WINCHELL, MICHAEL, A, SCHEEVEL, MARK, R
Year of Publication 17.07.1986

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Patent

System memory for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes

System memory for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes

by WINCHELL, MICHAEL A, LOGSDON, GARY L, SCHEEVEL, MARK R
Year of Publication 16.07.1986

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Patent

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