A programmable method for low-power scan shift in SoC integrated circuits
Ran Wang, Bhaskaran, Bonita, Natarajan, Karthikeyan, Abdollahian, Ayub, Narayanun, Kaushik, Chakrabarty, Krishnendu, Sanghani, Amit
Published in 2016 IEEE 34th VLSI Test Symposium (VTS) (01.04.2016)
Published in 2016 IEEE 34th VLSI Test Symposium (VTS) (01.04.2016)
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Conference Proceeding
Journal Article
Test method and scheme for low-power validation in modern SOC integrated circuits
Bhaskaran, Bonita, Sanghani, Amit, Narayanun, Kaushik, Abdollahian, Ayub, Laknaur, Amit
Published in 2016 IEEE 34th VLSI Test Symposium (VTS) (01.04.2016)
Published in 2016 IEEE 34th VLSI Test Symposium (VTS) (01.04.2016)
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Conference Proceeding
Journal Article
Flexible scan interface architecture for complex SoCs
Sonawane, Milind, Chadalavada, Sailendra, Sarangi, Shantanu, Sanghani, Amit, Yilmaz, Mahmut, Kumar Datla Jagannadha, Pavan, Colburn, Jonathon E.
Published in 2016 IEEE 34th VLSI Test Symposium (VTS) (01.04.2016)
Published in 2016 IEEE 34th VLSI Test Symposium (VTS) (01.04.2016)
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Conference Proceeding
Journal Article
Dynamic docking architecture for concurrent testing and peak power reduction
Sonawane, Milind, Jagannadha, Pavan Kumar Datla, Chadalavada, Sailendra, Sarangi, Shantanu, Yilmaz, Mahmut, Sanghani, Amit, Natarajan, Kathikeyan, Colburn, Jonathon E., Sinha, Anubhav
Published in 2016 IEEE 34th VLSI Test Symposium (VTS) (01.04.2016)
Published in 2016 IEEE 34th VLSI Test Symposium (VTS) (01.04.2016)
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Conference Proceeding
Journal Article
Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips
Sanghani, A, Bo Yang, Natarajan, K, Chunsheng Liu
Published in 29th VLSI Test Symposium (01.05.2011)
Published in 29th VLSI Test Symposium (01.05.2011)
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Conference Proceeding
Granular dynamic test systems and methods
Sonawane, Milind, Sarangi, Shantanu, Sanghani, Amit, Balagopala, Adarsh Kalliat
Year of Publication 19.11.2019
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Year of Publication 19.11.2019
Patent
Test architecture for die to die interconnect for three dimensional integrated circuits
Chakravarty, Sreejit, Tan, Terrence Huat Hin, Sanghani, Amit, B. S., Adithya, Sinha, Anubhav, Badana, Sudheer V, Kandula, Rakesh, Su, Fei, Lim, Wei Ming, Gupta, Puneet
Year of Publication 22.02.2022
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Year of Publication 22.02.2022
Patent
Scan systems and methods
Golshan Farideh, Sonawane Milind, Sanghani Amit, Kulkarni Ketan, Kottapalli Venkata
Year of Publication 06.02.2018
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Year of Publication 06.02.2018
Patent
GRANULAR DYNAMIC TEST SYSTEMS AND METHODS
SANGHANI Amit, SARANGI Shantanu, SONAWANE Milind, BALAGOPALA Adarsh Kalliat
Year of Publication 20.07.2017
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Year of Publication 20.07.2017
Patent
Granular dynamic test systems and methods
Sonawane, Milind, Sarangi, Shantanu, Colburn, Jonathon E, Chadalavada, Sailendra, Kumar reddy.S, Rajendra, Sanghani, Amit, Nelapatla, Bala Tarun
Year of Publication 28.01.2020
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Year of Publication 28.01.2020
Patent
Dynamic independent test partition clock
Sonawane, Milind, Sarangi, Shantanu, Natarajan, Karthikeyan, Jayaraman, Dheepakkumaran, Datla Jagannadha, Pavan Kumar, Sanghani, Amit, Sinha, Anubhav, Yilmaz, Mahmut
Year of Publication 12.11.2019
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Year of Publication 12.11.2019
Patent
Scan system interface (SSI) module
Sonawane, Milind, Sarangi, Shantanu, Colburn, Jonathon E, Kumar reddy.S, Rajendra, Sanghani, Amit, Chadalavda, Sailendra, Nelapatla, Bala Tarun
Year of Publication 11.06.2019
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Year of Publication 11.06.2019
Patent