Study of Chip Stacking Process and Electrical Characteristic Evaluation of Cu Pillar Joint Between Chips Including TSV
Akamatsu, Toshiya, Tadaki, Shinji, Yamazaki, Kazutoshi, Kitada, Hideki, Sakuyama, Seiki
Published in 2016 IEEE 66th Electronic Components and Technology Conference (ECTC) (01.05.2016)
Published in 2016 IEEE 66th Electronic Components and Technology Conference (ECTC) (01.05.2016)
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Conference Proceeding
Impact of 3D stacking on the TSV-induced stress and the CMOS characteristics
Dote, Aki, Tashiro, Hiroko, Kitada, Hideki, Tadaki, Shinji, Miyahara, Shoichi, Sakuyama, Seiki
Published in 2017 IEEE 19th Electronics Packaging Technology Conference (EPTC) (01.12.2017)
Published in 2017 IEEE 19th Electronics Packaging Technology Conference (EPTC) (01.12.2017)
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Conference Proceeding
Thermal stress reliability of copper through silicon via interconnects for 3D logic devices
Kitada, Hideki, Tashiro, Hiroko, Miyahara, Shoichi, Dote, Aki, Tadaki, Shinji, Sakuyama, Seiki
Published in 2016 IEEE 18th Electronics Packaging Technology Conference (EPTC) (01.11.2016)
Published in 2016 IEEE 18th Electronics Packaging Technology Conference (EPTC) (01.11.2016)
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Conference Proceeding