A CMOS bandgap reference circuit with sub-1-V operation
Banba, H., Shiga, H., Umezawa, A., Miyaba, T., Tanzawa, T., Atsumi, S., Sakui, K.
Published in IEEE journal of solid-state circuits (01.05.1999)
Published in IEEE journal of solid-state circuits (01.05.1999)
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Journal Article
Impact of Backside Defects on Device Characteristics of Ultra-Thin DRAMs with 3-5 μm Si Wafers for Bumpless Build Cube (BBCube) Application
Chen, Z., Araki, N., Kim, Y., Fukuda, T., Sakui, K., Nakamura, T., Kobayashi, T., Obara, T., Ohba, T.
Published in 2022 International Conference on Electronics Packaging (ICEP) (11.05.2022)
Published in 2022 International Conference on Electronics Packaging (ICEP) (11.05.2022)
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Conference Proceeding
A source-line programming scheme for low-voltage operation NAND flash memories
Takeuchi, K., Satoh, S., Imamiya, K., Sakui, K.
Published in IEEE journal of solid-state circuits (01.05.2000)
Published in IEEE journal of solid-state circuits (01.05.2000)
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Journal Article
A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory
Tanaka, T., Tanaka, Y., Nakamura, H., Sakui, K., Oodaira, H., Shirota, R., Ohuchi, K., Masuoka, F., Hara, H.
Published in IEEE journal of solid-state circuits (01.11.1994)
Published in IEEE journal of solid-state circuits (01.11.1994)
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Journal Article
A 120-mm/sup 2/ 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed
Jin-Ki Kim, Sakui, K., Sung-Soo Lee, Itoh, Y., Suk-Chon Kwon, Kanazawa, K., Ki-Jun Lee, Nakamura, H., Kang-Young Kim, Himeno, T., Jang-Rae Kim, Kanda, K., Tae-Sung Jung, Oshima, Y., Kang-Deog Suh, Hashimoto, K., Sung-Tae Ahn, Miyamoto, J.
Published in IEEE journal of solid-state circuits (01.05.1997)
Published in IEEE journal of solid-state circuits (01.05.1997)
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Journal Article
Quick address detection of anomalous memory cells in a flash memory test structure
Himeno, T., Hazama, H., Yaegashi, T., Sakui, K., Kanda, K., Itoh, Y., Miyamoto, J.
Published in IEEE transactions on semiconductor manufacturing (01.05.1997)
Published in IEEE transactions on semiconductor manufacturing (01.05.1997)
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Journal Article
Conference Proceeding
BiCMOS circuit technology for high-speed DRAMs
Watanabe, S., Sakui, K., Fuse, T., Hara, T., Aritome, S., Hieda, K.
Published in IEEE journal of solid-state circuits (01.01.1993)
Published in IEEE journal of solid-state circuits (01.01.1993)
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Journal Article
A new static memory cell based on the reverse base current effect of bipolar transistors
Sakui, K., Hasegawa, T., Fuse, T., Watanabe, S., Ohuchi, K., Masuoka, F.
Published in IEEE transactions on electron devices (01.06.1989)
Published in IEEE transactions on electron devices (01.06.1989)
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Journal Article
Noise-generation analysis and noise-suppression design techniques in megabit DRAMs
Itoh, Y., Nakagawa, K., Sakui, K., Horiguchi, F., Ogura, M.
Published in IEEE journal of solid-state circuits (01.08.1987)
Published in IEEE journal of solid-state circuits (01.08.1987)
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Journal Article
An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode
Watanabe, S., Oowaki, Y., Itoh, Y., Sakui, K., Numata, K., Fuse, T., Kobayashi, T., Tsuchida, K., Chiba, M., Hara, T., Ohta, M., Horiguchi, F., Hieda, K., Mitayama, A., Hamamoto, T., Ohuchi, K., Masuoka, F.
Published in IEEE journal of solid-state circuits (01.06.1989)
Published in IEEE journal of solid-state circuits (01.06.1989)
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Journal Article
A compact and low power logic design for multi-pillar vertical MOSFETs
Sakui, K, Endoh, T
Published in 2010 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2010)
Published in 2010 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2010)
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Conference Proceeding
A high-performance 1-Mbit dynamic RAM with a folded capacitor cell
Horiguchi, F., Ogura, M., Watanabe, S., Sakui, K., Miyawaki, N., Itoh, Y., Kurosawa, K., Masuoka, F., Iizuka, H.
Published in IEEE journal of solid-state circuits (01.12.1986)
Published in IEEE journal of solid-state circuits (01.12.1986)
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Journal Article
A quick address detection of an anomalous memory cell for flash EEPROM
Himeno, T., Hazama, H., Sakui, K., Kanda, K., Itoh, Y., Miyamoto, J.
Published in Proceedings of International Conference on Microelectronic Test Structures (1996)
Published in Proceedings of International Conference on Microelectronic Test Structures (1996)
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Conference Proceeding