The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips
Davidson, Scott, Xie, Shaolin, Torng, Christopher, Al-Hawai, Khalid, Rovinski, Austin, Ajayi, Tutu, Vega, Luis, Zhao, Chun, Zhao, Ritchie, Dai, Steve, Amarnath, Aporva, Veluri, Bandhav, Gao, Paul, Rao, Anuj, Liu, Gai, Gupta, Rajesh K., Zhang, Zhiru, Dreslinski, Ronald, Batten, Christopher, Taylor, Michael Bedford
Published in IEEE MICRO (01.03.2018)
Published in IEEE MICRO (01.03.2018)
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Journal Article
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator
Park, Dong-Hyeon, Pal, Subhankar, Feng, Siying, Gao, Paul, Tan, Jielun, Rovinski, Austin, Xie, Shaolin, Zhao, Chun, Amarnath, Aporva, Wesley, Timothy, Beaumont, Jonathan, Chen, Kuan-Yu, Chakrabarti, Chaitali, Taylor, Michael Bedford, Mudge, Trevor, Blaauw, David, Kim, Hun-Seok, Dreslinski, Ronald G.
Published in IEEE journal of solid-state circuits (01.04.2020)
Published in IEEE journal of solid-state circuits (01.04.2020)
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Journal Article
Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL
Rovinski, Austin, Veluri, Bandhav, Rao, Anuj, Ajayi, Tutu, Puscar, Julian, Dai, Steve, Zhao, Ritchie, Richmond, Dustin, Zhang, Zhiru, Galton, Ian, Batten, Christopher, Zhao, Chun, Taylor, Michael B., Dreslinski, Ronald G., Al-Hawaj, Khalid, Gao, Paul, Xie, Shaolin, Torng, Christopher, Davidson, Scott, Amarnath, Aporva, Vega, Luis
Published in IEEE solid-state circuits letters (01.12.2019)
Published in IEEE solid-state circuits letters (01.12.2019)
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Journal Article
Bridging Academic Open-Source EDA to Real-World Usability
Rovinski, Austin, Ajayi, Tutu, Kim, Minsoo, Wang, Guanru, Saligane, Mehdi
Published in 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD) (02.11.2020)
Published in 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD) (02.11.2020)
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Conference Proceeding
A carbon nanotube transistor based RISC-V processor using pass transistor logic
Amarnath, Aporva, Siying Feng, Pal, Subhankar, Ajayi, Tutu, Rovinski, Austin, Dreslinski, Ronald G.
Published in 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) (01.07.2017)
Published in 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) (01.07.2017)
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Conference Proceeding
Sirius Implications for Future Warehouse-Scale Computers
Hauswald, Johann, Laurenzano, Michael A., Yunqi Zhang, Cheng Li, Rovinski, Austin, Khurana, Arjun, Dreslinski, Ronald G., Mudge, Trevor, Petrucci, Vinicius, Lingjia Tang, Mars, Jason
Published in IEEE MICRO (01.05.2016)
Published in IEEE MICRO (01.05.2016)
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Journal Article
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm
Pal, Subhankar, Park, Dong-hyeon, Feng, Siying, Gao, Paul, Tan, Jielun, Rovinski, Austin, Xie, Shaolin, Zhao, Chun, Amarnath, Aporva, Wesley, Timothy, Beaumont, Jonathan, Chen, Kuan-Yu, Chakrabarti, Chaitali, Taylor, Michael, Mudge, Trevor, Blaauw, David, Kim, Hun-Seok, Dreslinski, Ronald
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
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Conference Proceeding
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm
Pal, Subhankar, Park, Dong-hyeon, Feng, Siying, Gao, Paul, Tan, Jielun, Rovinski, Austin, Xie, Shaolin, Zhao, Chun, Amarnath, Aporva, Wesley, Timothy, Beaumont, Jonathan, Chen, Kuan-Yu, Chakrabarti, Chaitali, Taylor, Michael, Mudge, Trevor, Blaauw, David, Kim, Hun-Seok, Dreslinski, Ronald
Published in 2019 Symposium on VLSI Technology (01.06.2019)
Published in 2019 Symposium on VLSI Technology (01.06.2019)
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Conference Proceeding
EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROAD
Wu, Bing-Yue, Sharma, Utsav, Kankipati, Sai Rahul Dhanvi, Yadav, Ajay, George, Bintu Kappil, Guntupalli, Sai Ritish, Rovinski, Austin, Chhabria, Vidya A.
Published in 2024 IEEE LLM Aided Design Workshop (LAD) (28.06.2024)
Published in 2024 IEEE LLM Aided Design Workshop (LAD) (28.06.2024)
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Conference Proceeding
EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROAD
Wu, Bing-Yue, Sharma, Utsav, Kankipati, Sai Rahul Dhanvi, Yadav, Ajay, George, Bintu Kappil, Guntupalli, Sai Ritish, Rovinski, Austin, Chhabria, Vidya A
Year of Publication 04.05.2024
Year of Publication 04.05.2024
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Journal Article
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS
Rovinski, Austin, Zhao, Chun, Al-Hawaj, Khalid, Gao, Paul, Xie, Shaolin, Torng, Christopher, Davidson, Scott, Amarnath, Aporva, Vega, Luis, Veluri, Bandhav, Rao, Anuj, Ajayi, Tutu, Puscar, Julian, Dai, Steve, Zhao, Ritchie, Richmond, Dustin, Zhang, Zhiru, Galton, Ian, Batten, Christopher, Taylor, Michael B, Dreslinski, Ronald G
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
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Conference Proceeding