A transitive closure algorithm for test generation
Chakradhar, S.T., Agrawal, V.D., Rothweiler, S.G.
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.07.1993)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.07.1993)
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Journal Article
Redundancy removal and test generation for circuits with non-Boolean primitives
Chakradhar, S.T., Rothweiler, S.G., Agrawal, V.D.
Published in Proceedings 13th IEEE VLSI Test Symposium (1995)
Published in Proceedings 13th IEEE VLSI Test Symposium (1995)
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Conference Proceeding
Sequential circuit delay optimization using global path delays
Chakradhar, Srimat T., Dey, Sujit, Potkonjak, Miodrag, Rothweiler, Steven G.
Published in 30th ACM/IEEE Design Automation Conference (01.07.1993)
Published in 30th ACM/IEEE Design Automation Conference (01.07.1993)
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Conference Proceeding
Bridge: a behavioral synthesis system for VLSI
Tseng, C.-J., Wei, R.-S., Rothweiler, S.G., Tog, M.M., Bose, A.K.
Published in Proceedings of the IEEE 1988 Custom Integrated Circuits Conference (1988)
Published in Proceedings of the IEEE 1988 Custom Integrated Circuits Conference (1988)
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Conference Proceeding