Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
Veloso, A., Jourdain, A., Radisic, D., Chen, R., Arutchelvan, G., O'Sullivan, B., Arimura, H., Stucchi, M., De Keersgieter, A., Hosseini, M., Hopf, T., D'have, K., Wang, S., Dupuy, E., Mannaert, G., Vandersmissen, K., Iacovo, S., Marien, P., Choudhury, S., Schleicher, F., Sebaai, F., Oniki, Y., Zhou, X., Gupta, A., Schram, T., Briggs, B., Lorant, C., Rosseel, E., Hikavyy, A., Loo, R., Geypen, J., Batuk, D., Martinez, G. T., Soulie, J. P., Devriendt, K., Chan, B. T., Demuynck, S., Hiblot, G., Van der Plas, G., Ryckaert, J., Beyer, G., Litta, E. Dentoni, Beyne, E., Horiguchi, N.
Published in IEEE transactions on electron devices (01.12.2022)
Published in IEEE transactions on electron devices (01.12.2022)
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First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers
Subramanian, S., Hosseini, M., Chiarella, T., Sarkar, S., Schuddinck, P., Chan, B. T., Radisic, D., Mannaert, G., Hikavyy, A., Rosseel, E., Sebaai, F., Peter, A., Hopf, T., Morin, P., Wang, S., Devriendt, K., Batuk, D., Martinez, G. T., Veloso, A., Litta, E. Dentoni, Baudot, S., Siew, Y. K., Zhou, X., Briggs, B., Capogreco, E., Hung, J., Koret, R., Spessot, A., Ryckaert, J., Demuynck, S., Horiguchi, N., Boemmels, J.
Published in 2020 IEEE Symposium on VLSI Technology (01.06.2020)
Published in 2020 IEEE Symposium on VLSI Technology (01.06.2020)
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Conference Proceeding
Methodology for Early Design Phase Cost and Performance Trade-Off Analysis of a New Variant in a Product Family
Schaffers, M., Rosseel, E., Burggraeve, S., Pelfrene, J., Gadeyne, K., Petré, F.
Published in Proceedings of the Design Society (01.05.2022)
Published in Proceedings of the Design Society (01.05.2022)
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3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability
Vandooren, A., Franco, J., Parvais, B., Wu, Z., Witters, L., Walke, A., Li, W., Peng, L., Deshpande, V., Bufler, F. M., Rassoul, N., Hellings, G., Jamieson, G., Inoue, F., Verbinnen, G., Devriendt, K., Teugels, L., Heylen, N., Vecchio, E., Zheng, T., Rosseel, E., Vanherle, W., Hikavyy, A., Chan, B. T., Ritzenthaler, R., Besnard, G., Schwarzenbach, W., Gaudin, G., Radu, I., Nguyen, B.-Y., Waldron, N., De Heyn, V., Mocuta, D., Collaert, N.
Published in IEEE transactions on electron devices (01.11.2018)
Published in IEEE transactions on electron devices (01.11.2018)
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Journal Article
Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates
Mertens, H., Ritzenthaler, R., Hikavyy, A., Kim, M. S., Tao, Z., Wostyn, K., Chew, S. A., De Keersgieter, A., Mannaert, G., Rosseel, E., Schram, T., Devriendt, K., Tsvetanova, D., Dekkers, H., Demuynck, S., Chasin, A., Van Besien, E., Dangol, A., Godny, S., Douhard, B., Bosman, N., Richard, O., Geypen, J., Bender, H., Barla, K., Mocuta, D., Horiguchi, N., Thean, A. V-Y
Published in 2016 IEEE Symposium on VLSI Technology (01.06.2016)
Published in 2016 IEEE Symposium on VLSI Technology (01.06.2016)
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Conference Proceeding
Properties and growth peculiarities of Si0.30Ge0.70 stressor integrated in 14nm fin-based p-type metal-oxide-semiconductor field-effect transistors
Hikavyy, A., Rosseel, E., Kubicek, S., Mannaert, G., Favia, P., Bender, H., Loo, R., Horiguchi, N.
Published in Thin solid films (01.03.2016)
Published in Thin solid films (01.03.2016)
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Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections
Vandooren, A., Parihar, N., Franco, J., Loo, R., Arimura, H., Rodriguez, R., Sebaai, F., Iacovo, S., Vandersmissen, K., Li, W., Mannaert, G., Radisic, D., Rosseel, E., Hikavyy, A., Jourdain, A., Mourey, O., Gaudin, G., Reboh, S., Van-Jodin, L. Le, Besnard, G., Neve, C. Roda, Nguyen, B-Y., Radu, I., Litta, E. Dentoni, Horiguchi, N.
Published in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (12.06.2022)
Published in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (12.06.2022)
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Conference Proceeding
Ni(Pt) silicide with improved thermal stability for application in DRAM periphery and replacement metal gate devices
Schram, T., Spessot, A., Ritzenthaler, R., Rosseel, E., Caillat, C., Horiguchi, N.
Published in Microelectronic engineering (25.05.2014)
Published in Microelectronic engineering (25.05.2014)
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3D Sequential Low Temperature Top Tier Devices using Dopant Activation with Excimer Laser Anneal and Strained Silicon as Performance Boosters
Vandooren, A., Wu, Z., Parihar, N., Franco, J., Parvais, B., Matagne, P., Debruyn, H., Mannaert, G., Devriendt, K., Teugels, L., Vecchio, E., Radisic, D., Rosseel, E., Hikavyy, A., Chan, B. T., Waldron, N., Mitard, J., Besnard, G., Alvarez, A., Gaudin, G., Schwarzenbach, W., Radu, I., Nguyen, B. Y., Huet, K., Tabata, T., Mazzamuto, F., Demuynck, S., Boemmels, J., Collaert, N., Horiguchi, N.
Published in 2020 IEEE Symposium on VLSI Technology (01.06.2020)
Published in 2020 IEEE Symposium on VLSI Technology (01.06.2020)
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Conference Proceeding
Ge instability and the growth of Ge epitaxial layers in nanochannels on patterned Si (001) substrates
Wang, G., Rosseel, E., Loo, R., Favia, P., Bender, H., Caymax, M., Heyns, M. M., Vandervorst, W.
Published in Journal of applied physics (15.12.2010)
Published in Journal of applied physics (15.12.2010)
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Journal Article
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
Veloso, A., Jourdain, A., Radisic, D., Chen, R., Arutchelvan, G., O'Sullivan, B., Arimura, H., Stucchi, M., Keersgieter, A. De, Hosseini, M., Hopf, T., D'Have, K., Wang, S., Dupuy, E., Mannaert, G., Vandersmissen, K., Iacovo, S., Marien, P., Choudhury, S., Schleicher, F., Sebaai, F., Oniki, Y., Zhou, X., Gupta, A., Schram, T., Briggs, B., Lorant, C., Rosseel, E., Hikavyy, A., Loo, R., Geypen, J., Batuk, D., Martinez, G. T., Soulie, J. P., Devriendt, K., Chan, B. T., Demuynck, S., Hiblot, G., der Plas, G. Van, Ryckaert, J., Beyer, G., Litta, E. Dentoni, Beyne, E., Horiguchi, N.
Published in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (12.06.2022)
Published in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (12.06.2022)
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Conference Proceeding
Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
Gupta, A., Mertens, H., Tao, Z., Demuynck, S., Bommels, J., Arutchelvan, G., Devriendt, K., Pedreira, O. Varela, Ritzenthaler, R., Wang, S., Radisic, D., Kenis, K., Teugels, L., Sebaai, F., Lorant, C., Jourdan, N., Chan, B. T., Zahedmanesh, H., Subramanian, S., Schleicher, F., Hopf, T., Peter, A., Rassoul, N., Debruyn, H., Demonie, I., Siew, Y., Chiarella, T., Briggs, B., Zhou, D., Rosseel, E., De Keersgieter, A., Capogreco, E., Litta, E. Dentoni, Boccardi, G., Baudot, S., Mannaert, G., Bontemps, N., Sepulveda, A., Mertens, S., Kim, M. S., Dupuy, E., Vandersmissen, K., Paolillo, S., Yakimets, D., Chehab, B., Favia, P., Drijbooms, C., Cousserier, J., Jaysankar, M., Lazzarino, F., Morin, P., Sanchez, E., Mitard, J., Wilson, C., Holsteyns, F., Tokei, Z., Horiguchi, N.
Published in 2020 IEEE Symposium on VLSI Technology (01.06.2020)
Published in 2020 IEEE Symposium on VLSI Technology (01.06.2020)
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Conference Proceeding
First demonstration of monocrystalline silicon macaroni channel for 3-D NAND memory devices
Delhougne, R., Arreghini, A., Rosseel, E., Hikavyy, A., Vecchio, E., Zhang, L., Pak, M., Nyns, L., Raymaekers, T., Jossart, N., Breuil, L., V-Palayam, S. S., Tan, C.-L., Van den bosch, G., Furnemont, A.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Conference Proceeding
Use of p- and n-type vapor phase doping and sub-melt laser anneal for extension junctions in sub-32 nm CMOS technology
Nguyen, N.D., Rosseel, E., Takeuchi, S., Everaert, J.-L., Yang, L., Goossens, J., Moussa, A., Clarysse, T., Richard, O., Bender, H., Zaima, S., Sakai, A., Loo, R., Lin, J.C., Vandervorst, W., Caymax, M.
Published in Thin solid films (01.01.2010)
Published in Thin solid films (01.01.2010)
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Web Resource
On the analysis of the activation mechanisms of sub-melt laser anneals
Clarysse, T., Bogdanowicz, J., Goossens, J., Moussa, A., Rosseel, E., Vandervorst, W., Petersen, D.H., Lin, R., Nielsen, P.F., Hansen, Ole, Merklin, G., Bennett, N.S., Cowern, N.E.B.
Published in Materials science & engineering. B, Solid-state materials for advanced technology (05.12.2008)
Published in Materials science & engineering. B, Solid-state materials for advanced technology (05.12.2008)
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New carbon-based thermal stability improvement technique for NiPtSi used in CMOS technology
Ortolland, C., Togo, M., Rosseel, E., Mertens, S., Kittl, J., Absil, P.P., Lauwers, A., Hoffmann, T.
Published in Microelectronic engineering (01.05.2011)
Published in Microelectronic engineering (01.05.2011)
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Conference Proceeding
Magnetization of multiple-quanta vortex lattices
Moshchalkov, VV, Baert, M, Metlushko, VV, Rosseel, E, Van Bael MJ, Temst, K, Jonckheere, R, Bruynseraede, Y
Published in Physical review. B, Condensed matter (01.09.1996)
Published in Physical review. B, Condensed matter (01.09.1996)
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Atomic Layer Deposition of Gd-Doped HfO[sub 2] Thin Films
Adelmann, C., Tielens, H., Dewulf, D., Hardy, A., Pierreux, D., Swerts, J., Rosseel, E., Shi, X., Van Bael, M. K., Kittl, J. A., Van Elshocht, S.
Published in Journal of the Electrochemical Society (2010)
Published in Journal of the Electrochemical Society (2010)
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A comparison of arsenic and phosphorus extension by Room Temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions
Sasaki, Y., Ritzenthaler, R., De Keersgieter, A., Chiarella, T., Kubicek, S., Rosseel, E., Waite, A., del Agua Borniquel, J., Colombeau, B., Chew, S. A., Kim, M. S., Schram, T., Demuynck, S., Vandervorst, W., Horiguchi, N., Mocuta, D., Mocuta, A., Thean, A. V.-Y
Published in 2015 Symposium on VLSI Technology (VLSI Technology) (01.06.2015)
Published in 2015 Symposium on VLSI Technology (VLSI Technology) (01.06.2015)
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