23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture
Kwangmyoung Rho, Tsuchida, Kenji, Dongkeun Kim, Shirai, Yutaka, Jihyae Bae, Inaba, Tsuneo, Noro, Hiromi, Hyunin Moon, Sungwoong Chung, Sunouchi, Kazumasa, Jinwon Park, Kiseon Park, Yamamoto, Akihito, Seoungju Chung, Hyeongon Kim, Oyamatsu, Hisato, Jonghoon Oh
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01.02.2017)
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01.02.2017)
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Conference Proceeding
Low Voltage and High Speed 1Xnm 1T1C FE-RAM with Ultra-Thin 5nm HZO
Sung, Minchul, Rho, Kwangmyoung, Kim, Jayong, Cheon, Junho, Choi, Kiyoung, Kim, Dohee, Em, Hoseok, Park, Gyeongcheol, Woo, Jungwook, Lee, Yeongyu, Ko, Jaehyeon, Kim, Moonhoi, Lee, Gwangyeob, Ryu, Seung Wook, Sheen, Dong Sun, Joo, Yangsung, Kim, Seiyon, Cho, Chang Hyun, Na, Myung-Hee, Kim, Jinkook
Published in 2021 IEEE International Electron Devices Meeting (IEDM) (11.12.2021)
Published in 2021 IEEE International Electron Devices Meeting (IEDM) (11.12.2021)
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Conference Proceeding
Three dimensional resistive memory architectures
Yi Jae Yun, Chung Sung Won, Rho Kwangmyoung, Kim Jeong Hwan, Perner Frederick, Hwang Sangmin, Park Jinwon, Lee Jae Yeon
Year of Publication 17.10.2017
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Year of Publication 17.10.2017
Patent
THREE DIMENSIONAL RESISTIVE MEMORY ARCHITECTURES
Yi Jae Yun, Chung Sung Won, Rho Kwangmyoung, Kim Jeong Hwan, Perner Frederick, Hwang Sangmin, Park Jinwon, Lee Jae Yeon
Year of Publication 25.08.2016
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Year of Publication 25.08.2016
Patent
THREE DIMENSIONAL RESISTIVE MEMORY ARCHITECTURES
YI, JAE YUN, CHUNG, SUNG WON, KIM, JEONG HWAN, PARK, JINWON, RHO, KWANGMYOUNG, PERNER, FREDERICK, HWANG, SANGMIN, LEE, JAE YEON
Year of Publication 07.05.2015
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Year of Publication 07.05.2015
Patent
Offset-Trimming Bit-Line Sensing Scheme for Gigabit-Scale DRAM's
Suh, Jungwon, Rho, Kwangmyoung, Park, Chankwang, Koh, Yohwan
Published in ESSCIRC '95: Twenty-first European Solid-State Circuits Conference (01.09.1995)
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Published in ESSCIRC '95: Twenty-first European Solid-State Circuits Conference (01.09.1995)
Conference Proceeding