Identification and classification of single-event upsets in the configuration memory of SRAM-based FPGAs
Ceschia, M., Violante, M., Reorda, M.S., Paccagnella, A., Bernardi, P., Rebaudengo, M., Bortolato, D., Bellato, M., Zambolin, P., Candelori, A.
Published in IEEE transactions on nuclear science (01.12.2003)
Published in IEEE transactions on nuclear science (01.12.2003)
Get full text
Journal Article
A new hybrid fault detection technique for systems-on-a-chip
Bernardi, P., Bolzani, L.M.V., Rebaudengo, M., Reorda, M.S., Vargas, F.L., Violante, M.
Published in IEEE transactions on computers (01.02.2006)
Published in IEEE transactions on computers (01.02.2006)
Get full text
Journal Article
Exploiting circuit emulation for fast hardness evaluation
Civera, P., Macchiarulo, L., Rebaudengo, M., Reorda, M.S., Violante, M.
Published in IEEE transactions on nuclear science (01.12.2001)
Published in IEEE transactions on nuclear science (01.12.2001)
Get full text
Journal Article
Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparison study
Rebaudengo, M., Reorda, M.S., Violante, M., Nicolescu, B., Velazco, R.
Published in IEEE transactions on nuclear science (01.06.2002)
Published in IEEE transactions on nuclear science (01.06.2002)
Get full text
Journal Article
Impact of data cache memory on the single event upset-induced error rate of microprocessors
Faure, F., Velazco, R., Violante, M., Rebaudengo, M., Reorda, M.S.
Published in IEEE transactions on nuclear science (01.12.2003)
Published in IEEE transactions on nuclear science (01.12.2003)
Get full text
Journal Article
Simulation-based analysis of SEU effects in SRAM-based FPGAs
Violante, M., Sterpone, L., Ceschia, M., Bortolato, D., Bernardi, P., Reorda, M.S., Paccagnella, A.
Published in IEEE transactions on nuclear science (01.12.2004)
Published in IEEE transactions on nuclear science (01.12.2004)
Get full text
Journal Article
DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study
Appello, D., Bernardi, P., Gerardin, S., Grosso, M., Paccagnella, A., Rech, P., Reorda, M.S.
Published in 2009 27th IEEE VLSI Test Symposium (01.05.2009)
Published in 2009 27th IEEE VLSI Test Symposium (01.05.2009)
Get full text
Conference Proceeding
Automatic test program generation: a case study
Corno, F., Sanchez, E., Reorda, M.S., Squillero, G.
Published in IEEE design & test of computers (01.03.2004)
Published in IEEE design & test of computers (01.03.2004)
Get full text
Journal Article
Test Program Generation for Communication Peripherals in Processor-Based SoC Devices
Apostolakis, A., Gizopoulos, D., Psarakis, M., Ravotto, D., Reorda, M.S.
Published in IEEE design & test of computers (01.03.2009)
Published in IEEE design & test of computers (01.03.2009)
Get full text
Journal Article
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Kastensmidt, F. Lima, Sterpone, L., Carro, L., Reorda, M. Sonza
Published in Design, Automation and Test in Europe (07.03.2005)
Published in Design, Automation and Test in Europe (07.03.2005)
Get full text
Conference Proceeding
System-in-package testing: problems and solutions
Appello, D., Bernardi, P., Grosso, M., Reorda, M.S.
Published in IEEE design & test of computers (01.05.2006)
Published in IEEE design & test of computers (01.05.2006)
Get full text
Journal Article
Low power BIST via non-linear hybrid cellular automata
Corno, F., Rebaudengo, M., Reorda, M.S., Squillero, G., Violante, M.
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Get full text
Conference Proceeding
An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores
Bernardi, Paolo, Sanchez, Edgar Ernesto SÁnchez, Schillaci, Massimiliano, Squillero, Giovanni, Sonza Reorda, Matteo
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.03.2008)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.03.2008)
Get full text
Journal Article
A new BIST architecture for low power circuits
Corno, F., Rebaudengo, M., Reorda, M.S., Violante, M.
Published in European Test Workshop 1999 (Cat. No.PR00390) (1999)
Published in European Test Workshop 1999 (Cat. No.PR00390) (1999)
Get full text
Conference Proceeding
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers
Get full text
Conference Proceeding
An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs
Reorda, M.S., Violante, M., Meinhardt, C., Reis, R.
Published in 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (01.10.2009)
Published in 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (01.10.2009)
Get full text
Conference Proceeding