Males and females with first episode psychosis present distinct profiles of social cognition and metacognition
Ferrer-Quintero, M., Fernández, D., López-Carrilero, R., Birulés, I., Barajas, A., Lorente-Rovira, E., Luengo, A., Díaz-Cutraro, L., Verdaguer, M., García-Mieres, H., Gutiérrez-Zotes, A., Grasa, E., Pousa, E., Huerta-Ramos, E., Pélaez, T., Barrigón, M. L., Gómez-Benito, J., González-Higueras, F., Ruiz-Delgado, I., Cid, J., Moritz, S., Sevilla-Llewellyn-Jones, J., Ochoa, S.
Published in European archives of psychiatry and clinical neuroscience (01.10.2022)
Published in European archives of psychiatry and clinical neuroscience (01.10.2022)
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Journal Article
Simulating Resistive-Bridging and Stuck-At Faults
Piet Engelke, Polian, I., Renovell, M., Becker, B.
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.10.2006)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.10.2006)
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Journal Article
Different experiments in test generation for XILINX FPGAs
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Conference Proceeding
Journal Article
Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis
Balen, T R, Calvano, J V, Lubaszewski, M S, Renovell, M
Published in Journal of electronic testing (01.12.2007)
Published in Journal of electronic testing (01.12.2007)
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Journal Article
Implementation of a linear histogram BIST for ADCs
Azais, F., Bernard, S., Bertrand, Y., Renovell, M.
Published in Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001 (2001)
Published in Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001 (2001)
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Conference Proceeding
Electrical analysis and modeling of floating-gate fault
Renovell, M., Cambon, G.N.
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.1992)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.1992)
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Journal Article
ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator
Kerzérho, V, Cauvet, P, Bernard, S, Azaïs, F, Renovell, M, Comte, M, Chakib, O
Published in VLSI Design (01.01.2008)
Published in VLSI Design (01.01.2008)
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Journal Article
Test of RAM-based FPGA: methodology and application to the interconnect
Renovell, M., Figueras, J., Zorian, Y.
Published in Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125) (1997)
Published in Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125) (1997)
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Conference Proceeding
A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs
Azaïs, F, Bernard, S, Bertrand, Y, Renovell, M
Published in Journal of electronic testing (01.04.2001)
Published in Journal of electronic testing (01.04.2001)
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Journal Article
Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short
Renovell, M, Gallière, Jm, Azaïs, F, Bertrand, Y
Published in Journal of electronic testing (01.08.2003)
Published in Journal of electronic testing (01.08.2003)
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Journal Article
A multi-configuration strategy for an application dependent testing of FPGAs
Tahoori, M.B., McCluskey, E.J., Renovell, M., Faure, P.
Published in 22nd IEEE VLSI Test Symposium, 2004. Proceedings (2004)
Published in 22nd IEEE VLSI Test Symposium, 2004. Proceedings (2004)
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Conference Proceeding
Fully digital test solution for a set of ADCs and DACs embedded in a SIP or SOC
KERZERHO, V, CAUVET, P, BERNARD, S, AZAÏS, F, COMTE, M, RENOVELL, M
Published in IET computers & digital techniques (01.05.2007)
Published in IET computers & digital techniques (01.05.2007)
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Conference Proceeding
Journal Article
Microsystems Testing: A Challenge
Renovell, M.
Published in Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259) (1998)
Published in Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259) (1998)
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Conference Proceeding
A compact DC model of gate oxide short defect
Bouchakour, R., Portal, J.M., Gallière, J.M., Azais, F., Bertrand, Y., Renovell, M.
Published in Microelectronic engineering (01.04.2004)
Published in Microelectronic engineering (01.04.2004)
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Journal Article
Conference Proceeding
A low-cost adaptive ramp generator for analog BIST applications
Azais, F., Bernard, S., Bertrand, Y., Michel, X., Renovell, M.
Published in Proceedings 19th IEEE VLSI Test Symposium. VTS 2001 (2001)
Published in Proceedings 19th IEEE VLSI Test Symposium. VTS 2001 (2001)
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Conference Proceeding
Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST
Azaïs, F, Bernard, S, Bertrand, Y, Renovell, M
Published in Journal of electronic testing (01.06.2001)
Published in Journal of electronic testing (01.06.2001)
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Journal Article
On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST
Bernard, S, Azaïs, F, Bertrand, Y, Renovell, M
Published in Journal of electronic testing (01.08.2003)
Published in Journal of electronic testing (01.08.2003)
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Journal Article