Automated construction of a cycle-approximate transaction level model of a memory controller
Todorov, Vladimir, Mueller-Gritschneder, Daniel, Reinig, Helmut, Schlichtmann, Ulf
Published in Proceedings of the Conference on Design, Automation and Test in Europe (12.03.2012)
Published in Proceedings of the Conference on Design, Automation and Test in Europe (12.03.2012)
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Conference Proceeding
An Efficient Weighted-Round-Robin Algorithm for Multiprocessor Architectures
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Conference Proceeding
Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs
Todorov, Vladimir, Ghiribaldi, Alberto, Reinig, Helmut, Bertozzi, Davide, Schlichtmann, Ulf
Published in Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis (07.10.2012)
Published in Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis (07.10.2012)
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Conference Proceeding