A low power high performance PLL with temperature compensated VCO in 65nm CMOS
Ravinuthula, V., Finocchiaro, S.
Published in 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) (01.05.2016)
Published in 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) (01.05.2016)
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Conference Proceeding
Time-mode circuits for analog computation
Ravinuthula, Vishnu, Garg, Vaibhav, Harris, John G., Fortes, José A. B.
Published in International journal of circuit theory and applications (01.06.2009)
Published in International journal of circuit theory and applications (01.06.2009)
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Journal Article
Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driver
Joy, A K, Mair, H, Hae-Chang Lee, Feldman, A, Portmann, C, Bulman, N, Crespo, E C, Hearne, P, Huang, P, Kerr, B, Khandelwal, P, Kuhlmann, F, Lytollis, S, Machado, J, Morrison, C, Morrison, S, Rabii, S, Rajapaksha, D, Ravinuthula, V, Surace, G
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)
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Conference Proceeding
Time-based arithmetic using step functions
Ravinuthula, V., Harris, J.G.
Published in 2004 IEEE International Symposium on Circuits and Systems (ISCAS) (2004)
Published in 2004 IEEE International Symposium on Circuits and Systems (ISCAS) (2004)
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Conference Proceeding