Circuit Level Realization of Low Latency Radix-4 Booth Scheme for Parallel Multipliers
Rahnamaei, Ali, Fatin, Gholamreza Zare
Published in National Academy of Sciences, India. Proceedings. Section A. Physical Sciences (2022)
Published in National Academy of Sciences, India. Proceedings. Section A. Physical Sciences (2022)
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Journal Article
Conference Proceeding
Numerical optimization of threshold voltage and off-current of a nano-scale symmetric double gate MOSFET based on the genetic algorithm: Various strategies compatible with device applications
Pashaki, Yazdan Karimi, Ziabari, Seyed Ali Sedigh, Eskandarian, Abdollah, Rahnamaei, Ali
Published in International journal of nano dimension (01.01.2023)
Published in International journal of nano dimension (01.01.2023)
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Journal Article
High Performance Low Latency 16×16 bit Booth Multiplier using Novel 4-2 Compressor Structure
Rahnamaei, Ali, Sarkaleh, Azadeh Kiani
Published in Majlesi journal of electrical engineering (01.06.2020)
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Published in Majlesi journal of electrical engineering (01.06.2020)
Journal Article
FPGA implementation of an ANN for detection of anthelmintics resistant nematodes in sheep flocks
Rahnamaei, A., Pariz, N., Akbarimajd, A.
Published in 2009 4th IEEE Conference on Industrial Electronics and Applications (01.05.2009)
Published in 2009 4th IEEE Conference on Industrial Electronics and Applications (01.05.2009)
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Conference Proceeding