(Invited) 3D-NAND Reliability: Review of key mechanisms and mitigations
Raghunathan, Shyam
Published in 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) (01.04.2020)
Published in 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) (01.04.2020)
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Conference Proceeding
PROGRAMMING MEMORIES WITH MULTI-LEVEL PASS SIGNAL
SRINIVASAN CHARAN, PARAT KRISHNA K, KALAVADE PRANAV, RAGHUNATHAN SHYAM SUNDER
Year of Publication 30.09.2019
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Year of Publication 30.09.2019
Patent
PROGRAMMING MEMORIES WITH MULTI-LEVEL PASS SIGNAL
SRINIVASAN CHARAN, PARAT KRISHNA K, KALAVADE PRANAV, RAGHUNATHAN SHYAM SUNDER
Year of Publication 22.03.2017
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Year of Publication 22.03.2017
Patent
DYNAMICALLY COMPENSATING FOR DEGRADATION OF A NON-VOLATILE MEMORY DEVICE
CHAO IWEN, PARAT KRISHNA K, GUO XIN, ZHU FENG, KALAVADE PRANAV, RAGHUNATHAN SHYAM SUNDER
Year of Publication 28.08.2017
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Year of Publication 28.08.2017
Patent
Novel SiGe Source/Drain for Reduced Parasitic Resistance in Ge NMOS
Raghunathan, Shyam, Krishnamohan, Tejas, Saraswat, Krishna C.
Published in ECS transactions (01.01.2010)
Published in ECS transactions (01.01.2010)
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Journal Article
Engineering of strained III-V heterostructures for high hole mobility
Nainani, A., Raghunathan, S., Witte, D., Kobayashi, M., Irisawa, T., Krishnamohan, T., Saraswat, K., Bennett, B.R., Ancona, M.G., Boos, J.B.
Published in 2009 IEEE International Electron Devices Meeting (IEDM) (01.12.2009)
Published in 2009 IEEE International Electron Devices Meeting (IEDM) (01.12.2009)
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Conference Proceeding
RAMPING INHIBIT VOLTAGE DURING MEMORY PROGRAMMING
MIELKE NEAL R, RAJWADE SHANTANU R, PARAT KRISHNA K, KALAVADE PRANAV, RAGHUNATHAN SHYAM SUNDER
Year of Publication 07.10.2015
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Year of Publication 07.10.2015
Patent
Comprehensive physics-based modeling of post-cycling long-term data retention in 176L 3-D NAND Flash Memories
Thakor, Karansingh, Rangarajan, Nikhil, Diwakar, Himanshu, Saikia, Rashmi, Samadder, Tarun, Mahapatra, Souvik, Raghunathan, Shyam, Dong, Yingda
Published in 2024 IEEE International Memory Workshop (IMW) (12.05.2024)
Published in 2024 IEEE International Memory Workshop (IMW) (12.05.2024)
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Conference Proceeding
BOOST-BY-DECK DURING A PROGRAM OPERATION ON A MEMORY DEVICE
Goda, Akira, Raimondo, Leo, Moschiano, Violante, Raghunathan, Shyam Sunder
Year of Publication 10.10.2024
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Year of Publication 10.10.2024
Patent
Partial block erase operations in memory devices
Moschiano, Violante, Raghunathan, Shyam Sunder, Che, Haiou, di Francesco, Walter
Year of Publication 10.09.2024
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Year of Publication 10.09.2024
Patent
DEFECT MANAGEMENT POLICIES FOR NAND FLASH MEMORY
ZHU, Feng, KALAVADE, Pranav, MOTWANI, Ravi H, RAGHUNATHAN, Shyam Sunder
Year of Publication 04.10.2023
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Year of Publication 04.10.2023
Patent
PARTIAL BLOCK ERASE OPERATIONS IN MEMORY DEVICES
Moschiano, Violante, Raghunathan, Shyam Sunder, Che, Haiou, di Francesco, Walter
Year of Publication 29.12.2022
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Year of Publication 29.12.2022
Patent
READ DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING
Righetti, Niccolo, Goda, Akira, Raimondo, Leo, Raghunathan, Shyam Sunder, Muccherla, Kishore K
Year of Publication 23.05.2024
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Year of Publication 23.05.2024
Patent
PROGRAMMING MEMORIES WITH MULTI-LEVEL PASS SIGNAL
KALAVADE, Pranav, SRINIVASAN, Charan, PARAT, Krishna K, RAGHUNATHAN, Shyam Sunder
Year of Publication 08.12.2021
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Year of Publication 08.12.2021
Patent
DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING
Malshe, Ashutosh, Goda, Akira, Muchherla, Kishore K, Raimondo, Leo, Huang, Jianmin, Luo, Xiangang, Raghunathan, Shyam Sunder, Hoei, Jung Sheng
Year of Publication 23.05.2024
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Year of Publication 23.05.2024
Patent