A scalable instruction queue design using dependence chains
Raasch, Steven E, Binkert, Nathan L, Reinhardt, Steven K
Published in ACM SIGARCH Computer Architecture News (01.05.2002)
Published in ACM SIGARCH Computer Architecture News (01.05.2002)
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Journal Article
A scalable instruction queue design using dependence chains
Raasch, Steven E., Binkert, Nathan L., Reinhardt, Steven K.
Published in Proceedings - International Symposium on Computer Architecture (01.05.2002)
Published in Proceedings - International Symposium on Computer Architecture (01.05.2002)
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Conference Proceeding
Lifetime memory reliability data from the field
Siddiqua, Taniya, Sridharan, Vilas, Raasch, Steven E., DeBardeleben, Nathan, Ferreira, Kurt B., Levy, Scott, Baseman, Elisabeth, Qiang Guan
Published in 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (01.10.2017)
Published in 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (01.10.2017)
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Conference Proceeding
Memory access response merging in a memory hierarchy
Kayiran, Onur, Eckert, Yasuko, Kazakov, Maxim V, Oskin, Mark Henry, Raasch, Steven E, Loh, Gabriel H
Year of Publication 02.08.2022
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Year of Publication 02.08.2022
Patent
MEMORY ACCESS RESPONSE MERGING IN A MEMORY HIERARCHY
Kayiran, Onur, Eckert, Yasuko, Kazakov, Maxim V, Oskin, Mark Henry, Raasch, Steven E, Loh, Gabriel H
Year of Publication 24.03.2022
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Year of Publication 24.03.2022
Patent
Using Predictions of Outcomes of Cache Memory Access Requests for Contolling Whether A Request Generator Sends Memory Access Requests To A Memory In Parallel With Cache Memory Access Requests
Yin, Jieming, Eckert, Yasuko, Poremba, Matthew R, Hunt, Doug, Raasch, Steven E
Year of Publication 13.08.2020
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Year of Publication 13.08.2020
Patent
Controlling non-redundant execution in a redundant multithreading (RMT) processor
Singhal Ronak, Holm John G, Marr Deborah T, Sodani Avinash, Hinton Glenn J, Hily Sebastien, Raasch Steven E
Year of Publication 14.03.2017
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Year of Publication 14.03.2017
Patent
Redundant multithreading processor
MARR DEBORAH T, SODANI AVINASH, HILY SEBASTIEN, HOLM JOHN G, HINTON GLENN J, RAASCH STEVEN E, SINGHAL RONAK
Year of Publication 29.07.2014
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Year of Publication 29.07.2014
Patent
Obtaining data for redundant multithreading (RMT) execution
MARR DEBORAH T, SODANI AVINASH, HILY SEBASTIEN, HOLM JOHN G, HINTON GLENN J, BISWAS ARIJIT, MUKHERJEE SHUBHENDU S, RAASCH STEVEN E, MOGA ADRIAN C, SINGHAL RONAK
Year of Publication 14.07.2015
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Year of Publication 14.07.2015
Patent
State history storage for synchronizing redundant processors
Mukherjee, Shubhendu S, Biswas, Arijit, Racunas, Paul B, Raasch, Steven E
Year of Publication 01.05.2012
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Year of Publication 01.05.2012
Patent
State history storage for synchronizing redundant processors
RACUNAS PAUL B, BISWAS ARIJIT, MUKHERJEE SHUBHENDU S, RAASCH STEVEN E
Year of Publication 01.05.2012
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Year of Publication 01.05.2012
Patent
Redundant Multithreading Processor
MARR DEBORAH T, SODANI AVINASH, HILY SEBASTIEN, HOLM JOHN G, HINTON GLENN J, RAASCH STEVEN E, SINGHAL RONAK
Year of Publication 15.12.2011
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Year of Publication 15.12.2011
Patent
STATE HISTORY STORAGE FOR SYNCHRONIZING REDUNDANT PROCESSORS
RACUNAS PAUL B, BISWAS ARIJIT, MUKHERJEE SHUBHENDU S, RAASCH STEVEN E
Year of Publication 01.07.2010
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Year of Publication 01.07.2010
Patent
Reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system
Racunas, Paul B, Emer, Joel S, Biswas, Arijit, Mukherjee, Shubhendu S, Raasch, Steven E
Year of Publication 29.06.2010
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Year of Publication 29.06.2010
Patent