Search Results - "ROUH, KYOUNG BONG" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

METHOD OF IMPLANTING P-TYPE ION IMPURITIES IN DUAL POLY-GATE AND METHOD OF FABRICATING DUAL POLY GATE USING THE SAME

METHOD OF IMPLANTING P-TYPE ION IMPURITIES IN DUAL POLY-GATE AND METHOD OF FABRICATING DUAL POLY GATE USING THE SAME

by ROUH, KYOUNG BONG
Year of Publication 23.12.2010

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Patent

METHOD FOR FABRICATING PMOS TRANSISTOR

METHOD FOR FABRICATING PMOS TRANSISTOR

by ROUH, KYOUNG BONG
Year of Publication 06.07.2010

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Patent

APPARATUS AND METHOD FOR PARTIAL ION IMPLANTATION USING ATOM VIBRATION

APPARATUS AND METHOD FOR PARTIAL ION IMPLANTATION USING ATOM VIBRATION

by ROUH, KYOUNG BONG
Year of Publication 03.11.2009

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Patent

DOPING METHOD FOR P-TYPE POLY-GATE FOR PREVENTING SEAM MOVING AND METHOD OF FABRICATING THE POLY-GATE USING THE SAME

DOPING METHOD FOR P-TYPE POLY-GATE FOR PREVENTING SEAM MOVING AND METHOD OF FABRICATING THE POLY-GATE USING THE SAME

by KIM, TAE KYUN, ROUH, KYOUNG BONG
Year of Publication 23.12.2010

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Patent

SEMICONDUCTOR DEVICE AND THE METHOD FOR MANUFACTURING THE SAME

SEMICONDUCTOR DEVICE AND THE METHOD FOR MANUFACTURING THE SAME

by KIM, TAE KYUN, ROUH, KYOUNG BONG
Year of Publication 08.07.2010

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Patent

TRANSISTOR CONTROLLING SHORT CHANNEL EFFECT AND THE METHOD OF MANUFACTURING THE SAME

TRANSISTOR CONTROLLING SHORT CHANNEL EFFECT AND THE METHOD OF MANUFACTURING THE SAME

by JOO, YOUNG HWAN, ROUH, KYOUNG BONG
Year of Publication 20.05.2010

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Patent

METHOD OF DOPING P-TYPE IMPURITY IONS IN DUAL POLY GATE AND FORMING THE DUAL POLY GATE USING THE SAME

METHOD OF DOPING P-TYPE IMPURITY IONS IN DUAL POLY GATE AND FORMING THE DUAL POLY GATE USING THE SAME

by LEE, SEUNG MI, ROUH, KYOUNG BONG
Year of Publication 23.12.2010

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Patent

METHOD OF FORMING EXTENDED HALO REGION IN MOS TRANSISTOR

METHOD OF FORMING EXTENDED HALO REGION IN MOS TRANSISTOR

by LEE, SEUNG MI, ROUH, KYOUNG BONG
Year of Publication 11.08.2010

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Patent

METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE HAVING GATE SPACER LAYER WITH UNIFORM THICKNESS

METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE HAVING GATE SPACER LAYER WITH UNIFORM THICKNESS

by SEO, HYE JIN, ROUH, KYOUNG BONG, JUNG, YONG SOO
Year of Publication 02.07.2009

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Patent

METHOD FOR FABRICATING PMOS TRANSISTOR AND METHOD FOR FORMING DUAL GATE OF SEMICONDUCTOR DEVICE

METHOD FOR FABRICATING PMOS TRANSISTOR AND METHOD FOR FORMING DUAL GATE OF SEMICONDUCTOR DEVICE

by KIM, CHOON HWAN, ROUH, KYOUNG BONG, RHO, IL CHEOL
Year of Publication 20.05.2010

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Patent

METHOD OF FABRICATING CONTACT IN SEMICONDUCTOR DEVICE

METHOD OF FABRICATING CONTACT IN SEMICONDUCTOR DEVICE

by KIM, CHOON HWAN, ROUH, KYOUNG BONG, RHO, IL CHEOL
Year of Publication 07.07.2009

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Patent

METHOD OF DOPING IMPURITY IONS IN DUAL GATE AND METHOD OF FABRICATING THE DUAL GATE USING THE SAME

METHOD OF DOPING IMPURITY IONS IN DUAL GATE AND METHOD OF FABRICATING THE DUAL GATE USING THE SAME

by KIM, TAE KYUN, LEE, SEUNG MI, ROUH, KYOUNG BONG, JI, YUN HYUCK, KIM, WOO SUNG
Year of Publication 17.11.2010

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Patent

TRANSISTOR WITH ASYMMETRICALLY FORMED SOURCE AND DRAIN REGION IN SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF

TRANSISTOR WITH ASYMMETRICALLY FORMED SOURCE AND DRAIN REGION IN SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF

by JIN, SEUNG WOO, KIM, BONG SOO, ROUH, KYOUNG BONG
Year of Publication 10.03.2005

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Patent

METHOD FOR FABRICATING CELL OF SEMICONDUCTOR MEMORY DEVICE TO PREVENT CHANNELING EFFECT AND INCREASE REFRESH OF DRAM DEVICE

METHOD FOR FABRICATING CELL OF SEMICONDUCTOR MEMORY DEVICE TO PREVENT CHANNELING EFFECT AND INCREASE REFRESH OF DRAM DEVICE

by JIN, SEUNG WOO, KIM, BONG SOO, ROUH, KYOUNG BONG
Year of Publication 07.01.2005

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Patent

Integration of Low Resistive CVD-W Interconnects for sub-50nm FEOL application

Integration of Low Resistive CVD-W Interconnects for sub-50nm FEOL application

by Kim, Choon-Hwan, Rho, Il-Cheol, Rouh, Kyoung-Bong, Lim, Kwan-Yong, Kim, Yong-Soo, Ku, Ja-Chun, Sohn, Yong-Sun, Kang, Hyo-Sang, Kim, Hyeong-Joon
Published in 2008 International Interconnect Technology Conference (01.06.2008)

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Conference Proceeding

MOS transistor suppressing short channel effect and method of fabricating the same

MOS transistor suppressing short channel effect and method of fabricating the same

by ROUH KYOUNG BONG
Year of Publication 12.08.2014

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Patent

Method of fabricating a landing plug in a semiconductor device

Method of fabricating a landing plug in a semiconductor device

by ROUH KYOUNG BONG
Year of Publication 04.12.2012

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Patent

Method of fabricating a landing plug in a semiconductor device

Method of fabricating a landing plug in a semiconductor device

by Rouh, Kyoung Bong
Year of Publication 04.12.2012

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Patent

MOS TRANSISTOR SUPPRESSING SHORT CHANNEL EFFECT AND METHOD OF FABRICATING THE SAME

MOS TRANSISTOR SUPPRESSING SHORT CHANNEL EFFECT AND METHOD OF FABRICATING THE SAME

by ROUH KYOUNG BONG
Year of Publication 08.11.2012

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Patent

Method of fabricating a MOS transistor having a gate insulation layer with a lateral portion and a vertical portion

Method of fabricating a MOS transistor having a gate insulation layer with a lateral portion and a vertical portion

by Rouh, Kyoung-Bong
Year of Publication 17.07.2012

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Patent

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