Pothole detection in bituminous road using CNN with transfer learning
Vinodhini, Kanchi Anantharaman, Sidhaarth, Kovilvenni Ramachandran Aswin
Published in Measurement. Sensors (01.02.2024)
Published in Measurement. Sensors (01.02.2024)
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Journal Article
A Decentralized Context Broker Using Byzantine Fault Tolerant Consensus
Ramachandran Venkatapathy, Aswin Karthik, Ten Hompel, Michael
Published in Ledger (Pittsburgh, Pa.) (01.01.2019)
Published in Ledger (Pittsburgh, Pa.) (01.01.2019)
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Journal Article
Decentralized brain in low data-rate, low power networks for collaborative manoeuvres in space
Ramachandran Venkatapathy, Aswin Karthik, Ekblaw, Ariel, ten Hompel, Michael, Paradiso, Joseph
Published in 2018 6th IEEE International Conference on Wireless for Space and Extreme Environments (WiSEE) (01.12.2018)
Published in 2018 6th IEEE International Conference on Wireless for Space and Extreme Environments (WiSEE) (01.12.2018)
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Conference Proceeding
PhyNetLab: An IoT-Based Warehouse Testbed
Falkenberg, Robert, Masoudinejad, Mojtaba, Buschhoff, Markus, Aswin Karthik Ramachandran Venkatapathy, Friesel, Daniel, Michael ten Hompel, Spinczyk, Olaf, Wietfeld, Christian
Published in arXiv.org (28.06.2017)
Published in arXiv.org (28.06.2017)
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Paper
Journal Article
Mechanism to enter or exit retention level voltage while a system-on-a-chip is in low power mode
Crews, Darren S, Lu, Chin Seng, Bibikar, Vasudev, Ramachandran, Aswin, Rajesh, Moorthy
Year of Publication 25.08.2020
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Year of Publication 25.08.2020
Patent
MECHANISM TO ENTER OR EXIT RETENTION LEVEL VOLTAGE WHILE A SYSTEM-ON-A-CHIP IS IN LOW POWER MODE
LU, Chin Seng, BIBIKAR, Vasudev, RAJESH, Moorthy, CREWS, Darren, RAMACHANDRAN, Aswin
Year of Publication 04.04.2019
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Year of Publication 04.04.2019
Patent
MECHANISM TO ENTER OR EXIT RETENTION LEVEL VOLTAGE WHILE A SYSTEM-ON-A-CHIP IS IN LOW POWER MODE
Crews, Darren S, Lu, Chin Seng, Bibikar, Vasudev, Ramachandran, Aswin, Rajesh, Moorthy
Year of Publication 04.04.2019
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Year of Publication 04.04.2019
Patent
MECHANISM TO ENTER OR EXIT RETENTION LEVEL VOLTAGE WHILE A SYSTEM-ON-A-CHIP IS IN LOW POWER MODE
RAJESH MOORTHY, BIBIKAR VASUDEV, LU CHIN SENG, RAMACHANDRAN ASWIN, CREWS DARREN S
Year of Publication 24.04.2020
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Year of Publication 24.04.2020
Patent