Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology
Kim, Yusung, Ong, Clifford, Pillai, Anandkumar Mahadevan, Jagadeesh, Harish, Baek, Gwanghyeon, Rajwani, Iqbal, Guo, Zheng, Karl, Eric
Published in IEEE journal of solid-state circuits (01.04.2023)
Published in IEEE journal of solid-state circuits (01.04.2023)
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Journal Article
Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology
Kim, Yusung, Ong, Clifford, Pillai, Anandkumar Mahadevan, Jagadeesh, Harish, Baek, Gwanghyeon, Rajwani, Iqbal, Guo, Zheng, Karl, Eric
Published in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (12.06.2022)
Published in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (12.06.2022)
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Conference Proceeding
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Year of Publication 08.02.2024
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Year of Publication 08.02.2024
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Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing
Gomes, Wilfred, Koker, Altug, Stover, Pat, Ingerly, Doug, Siers, Scott, Venkataraman, Srikrishnan, Pelto, Chris, Shah, Tejas, Rao, Amreesh, O'Mahony, Frank, Karl, Eric, Cheney, Lance, Rajwani, Iqbal, Jain, Hemant, Cortez, Ryan, Chandrasekhar, Arun, Kanthi, Basavaraj, Koduri, Raja
Published in 2022 IEEE International Solid- State Circuits Conference (ISSCC) (20.02.2022)
Published in 2022 IEEE International Solid- State Circuits Conference (ISSCC) (20.02.2022)
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Conference Proceeding
ENERGY EFFICIENT MEMORY ARRAY WITH OPTIMIZED BURST READ AND WRITE DATA ACCESS AND SCHEME FOR READING AND WRITING DATA FROM/TO REARRANGED MEMORY SUBARRAY WHERE UNUSED METADATA IS STORED IN A SPARSITY MAP
KOKER ALTUG, AUGUSTINE CHARLES, STRIRAMASSARMA LAKSHMINARAYANAN, LINES ANDREW, MAJUMDER TURBO, KHELLAH MUHAMMAD, RAJWANI IQBAL, PAUL SOMNATH
Year of Publication 01.07.2021
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Year of Publication 01.07.2021
Patent
Dynamic power budget allocation in multi-processor system
Borole, Bhushan, Jahagirdar, Sanjeev, Sinha, Kamal, Kaburlasos, Nikos, Rajwani, Iqbal
Year of Publication 16.01.2024
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Year of Publication 16.01.2024
Patent
DYNAMIC POWER BUDGET ALLOCATION IN MULTI-PROCESSOR SYSTEM
Borole, Bhushan, Jahagirdar, Sanjeev, Sinha, Kamal, Kaburlasos, Nikos, Rajwani, Iqbal
Year of Publication 02.02.2023
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Year of Publication 02.02.2023
Patent
Dynamic power budget allocation in multi-processor system
Borole, Bhushan, Jahagirdar, Sanjeev, Sinha, Kamal, Kaburlasos, Nikos, Rajwani, Iqbal
Year of Publication 08.11.2022
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Year of Publication 08.11.2022
Patent
DYNAMIC POWER BUDGET ALLOCATION IN MULTI-PROCESSOR SYSTEM
Borole, Bhushan, Jahagirdar, Sanjeev, Sinha, Kamal, Kaburlasos, Nikos, Rajwani, Iqbal
Year of Publication 04.03.2021
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Year of Publication 04.03.2021
Patent
Disaggregation of system-on-chip (SOC) architecture
Cheney, Lance, Teshome, Melaku, Matam, Naveen, Koker, Altug, Xavier, Binoj, Jahagirdar, Sanjeev, Finley, Eric, Mastronarde, Josh, George, Varghese, Striramassarma, Lakshminarayanan, Rajwani, Iqbal, Vemulapalli, Vikranth
Year of Publication 06.08.2024
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Year of Publication 06.08.2024
Patent
DISAGGREGATION OF SOC ARCHITECTURE
Cheney, Lance, Teshome, Melaku, Matam, Naveen, Koker, Altug, Xavier, Binoj, Jahagirdar, Sanjeev, Finley, Eric, Mastronarde, Josh, George, Varghese, Striramassarma, Lakshminarayanan, Rajwani, Iqbal, Vemulapalli, Vikranth
Year of Publication 03.07.2024
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Year of Publication 03.07.2024
Patent
DISAGGREGATION OF SOC ARCHITECTURE
Cheney, Lance, Teshome, Melaku, Matam, Naveen, Koker, Altug, Xavier, Binoj, Jahagirdar, Sanjeev, Finley, Eric, Mastronarde, Josh, George, Varghese, Striramassarma, Lakshminarayanan, Rajwani, Iqbal, Vemulapalli, Vikranth
Year of Publication 15.05.2024
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Year of Publication 15.05.2024
Patent
Dynamic power budget allocation in multi-processor system
Borole, Bhushan, Jahagirdar, Sanjeev, Sinha, Kamal, Kaburlasos, Nikos, Rajwani, Iqbal
Year of Publication 18.08.2020
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Year of Publication 18.08.2020
Patent
DISAGGREGATION OF SOC ARCHITECTURE
Cheney, Lance, Teshome, Melaku, Matam, Naveen, Koker, Altug, Xavier, Binoj, Jahagirdar, Sanjeev, Finley, Eric, Mastronarde, Josh, George, Varghese, Striramassarma, Lakshminarayanan, Rajwani, Iqbal, Vemulapalli, Vikranth
Year of Publication 28.02.2024
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Year of Publication 28.02.2024
Patent
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
Cheney, Lance, Teshome, Melaku, Matam, Naveen, Koker, Altug, Xavier, Binoj, Jahagirdar, Sanjeev, Finley, Eric, Mastronarde, Josh, George, Varghese, Striramassarma, Lakshminarayanan, Rajwani, Iqbal, Vemulapalli, Vikranth
Year of Publication 11.01.2024
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Year of Publication 11.01.2024
Patent
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
Cheney, Lance, Teshome, Melaku, Matam, Naveen, Koker, Altug, Xavier, Binoj, Jahagirdar, Sanjeev, Finley, Eric, Mastronarde, Josh, George, Varghese, Striramassarma, Lakshminarayanan, Rajwani, Iqbal, Vemulapalli, Vikranth
Year of Publication 04.01.2024
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Year of Publication 04.01.2024
Patent
Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS
Hsu, Steven, Agarwal, Amit, Realov, Simeon, Anders, Mark, Chen, Gregory, Kar, Monodeep, Kumar, Raghavan, Sumbul, Huseyin, Knag, Phil, Kaul, Himanshu, Suresh, Vikram, Mathew, Sanu, Rajwani, Iqbal, Damaraju, Satish, Krishnamurthy, Ram, De, Vivek
Published in 2020 IEEE Symposium on VLSI Circuits (01.06.2020)
Published in 2020 IEEE Symposium on VLSI Circuits (01.06.2020)
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Conference Proceeding
Disaggregation of system-on-chip (SOC) architecture
Cheney, Lance, Teshome, Melaku, Matam, Naveen, Koker, Altug, Xavier, Binoj, Jahagirdar, Sanjeev, Finley, Eric, Mastronarde, Josh, George, Varghese, Striramassarma, Lakshminarayanan, Rajwani, Iqbal, Vemulapalli, Vikranth
Year of Publication 19.09.2023
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Year of Publication 19.09.2023
Patent